| Line 31... |
Line 31... |
`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
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`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
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`define NMI_VECTOR 64'hFFFF_FFFF_FFFF_FFE0
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`define NMI_VECTOR 64'hFFFF_FFFF_FFFF_FFE0
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`define IRQ_VECTOR 64'hFFFF_FFFF_FFFF_FFD0
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`define IRQ_VECTOR 64'hFFFF_FFFF_FFFF_FFD0
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`define TRAP_VECTOR 64'h0000_0000_0000_0000
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`define TRAP_VECTOR 64'h0000_0000_0000_0000
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`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
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`define ITLB_MissHandler 64'hFFFF_FFFF_FFFF_FFC0
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`define ITLB_MissHandler 64'hFFFF_FFFF_FFFF_FFC0
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`define DTLB_MissHandler 64'hFFFF_FFFF_FFFF_FFB0
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`define DTLB_MissHandler 64'hFFFF_FFFF_FFFF_FFB0
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`define BERR_VECTOR 64'hFFFF_FFFF_FFFF_FFA0
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`define GEN_TRAP_OFFSET 13'h0200
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`define DBZ_TRAP_OFFSET 13'h0050
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`define OFL_TRAP_OFFSET 13'h0070
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`define PRIV_OFFSET 13'h0080
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`define EX_NON 9'd000
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`define EX_NON 9'd000
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`define EX_TRAP 9'd32 // Trap exception
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`define EX_TRAP 9'd32 // Trap exception
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`define EX_IRQ 9'd449 // interrupt
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`define EX_IRQ 9'd449 // interrupt
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`define EX_DBZ 9'd488 // divide by zero
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`define EX_DBZ 9'd488 // divide by zero
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| Line 54... |
Line 47... |
`define EX_DBERR 9'd508 // Bus Error - load or store or I/O
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`define EX_DBERR 9'd508 // Bus Error - load or store or I/O
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`define EX_IBERR 9'd509 // Bus Error - instruction fetch
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`define EX_IBERR 9'd509 // Bus Error - instruction fetch
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`define EX_NMI 9'd510 // non-maskable interrupt
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`define EX_NMI 9'd510 // non-maskable interrupt
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`define EX_RST 9'd511 // Reset
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`define EX_RST 9'd511 // Reset
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`define EXCEPT_Int 5'd00
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`include "Raptor64_opcodes.v"
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`define EXCEPT_Mod 5'd01 // TLB modification
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`define EXCEPT_TLBL 5'd02 // TLB exception - load or ifetch
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`define EXCEPT_TLBS 5'd03 // TLB exception - store
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`define EXCEPT_AdEL 5'd04 // Address error - load or ifetch
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`define EXCEPT_AdES 5'd05 // Address error - store
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`define EXCEPT_IBE 5'd06 // Bus Error - instruction fetch
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`define EXCEPT_DBE 5'd07 // Bus Error - load or store
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`define EXCEPT_Sys 5'd08
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`define EXCEPT_Bp 5'd09
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`define EXCEPT_RI 5'd10 // reserved instruction
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`define EXCEPT_CpU 5'd11 // Coprocessor unusable
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`define EXCEPT_Ov 5'd12 // Integer Overflow
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`define EXCEPT_Tr 5'd13 // Trap exception
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// 14-22 Reserved
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`define EXCEPT_WATCH 5'd23
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`define EXCEPT_MCheck 5'd24 // Machine check
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// 25-31 Reserved
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`define MISC 7'd0
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`define BRK 7'd0
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`define IRQ 7'd1
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`define ICACHE_ON 7'd10
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`define ICACHE_OFF 7'd11
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`define DCACHE_ON 7'd12
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`define DCACHE_OFF 7'd13
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`define FIP 7'd20
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`define SYSJMP 7'd22
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`define SYSCALL 7'd23
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`define IRET 7'd32
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`define ERET 7'd33
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`define WAIT 7'd40
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`define TLBP 7'd49
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`define TLBR 7'd50
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`define TLBWI 7'd51
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`define TLBWR 7'd52
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`define CLI 7'd64
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`define SEI 7'd65
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`define GRAN 7'd80
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`define GRAFD 7'd82
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`define R 7'd1
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`define COM 7'd4
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`define NOT 7'd5
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`define NEG 7'd6
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`define ABS 7'd7
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`define SGN 7'd8
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`define MOV 7'd9
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`define SWAP 7'd13
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`define CTLZ 7'd16
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`define CTLO 7'd17
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`define CTPOP 7'd18
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`define SEXT8 7'd19
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`define SEXT16 7'd20
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`define SEXT32 7'd21
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`define SQRT 7'd24
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`define REDOR 7'd30
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`define REDAND 7'd31
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`define MFSPR 7'd40
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`define MTSPR 7'd41
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`define SR 6'd00
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`define TLBIndex 6'd01
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`define TLBRandom 6'd02
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`define PageTableAddr 6'd04
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`define BadVAddr 6'd08
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`define TLBPhysPage0 6'd10
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`define TLBPhysPage1 6'd11
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`define TLBVirtPage 6'd12
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`define TLBPageMask 6'd13
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`define TLBASID 6'd14
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`define ASID 6'd15
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`define Wired 6'd16
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`define EP0 6'd17
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`define EP1 6'd18
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`define EP2 6'd19
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`define EP3 6'd20
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`define AXC 6'd21
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`define Tick 6'd22
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`define EPC 6'd23
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`define CauseCode 6'd24
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`define TBA 6'd25
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`define NON_ICACHE_SEG 6'd26
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`define FPCR 6'd32
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`define IPC 6'd33
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`define RAND 6'd34
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`define SRANDZ 6'd35
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`define SRANDW 6'd36
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`define INSNKEY 6'd37
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`define OMG 7'd50
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`define CMG 7'd51
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`define OMGI 7'd52
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`define CMGI 7'd53
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`define EXEC 7'd58
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`define MYST 7'd59
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`define RR 7'd2
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`define ADD 7'd2
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`define ADDU 7'd3
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`define SUB 7'd4
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`define SUBU 7'd5
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`define CMP 7'd6
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`define CMPU 7'd7
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`define AND 7'd8
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`define OR 7'd9
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`define XOR 7'd10
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`define ANDC 7'd11
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`define NAND 7'd12
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`define NOR 7'd13
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`define XNOR 7'd14
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`define ORC 7'd15
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`define MIN 7'd20
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`define MAX 7'd21
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`define MULU 7'd24
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`define MULS 7'd25
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`define DIVU 7'd26
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`define DIVS 7'd27
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`define MOD 7'd28
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`define MOVZ 7'd30
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`define MOVNZ 7'd31
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`define SHL 7'd40
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`define SHRU 7'd41
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`define ROL 7'd42
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`define ROR 7'd43
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`define SHR 7'd44
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`define ROLAM 7'd45
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`define NOP 7'd60
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`define SLT 7'd96
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`define SLE 7'd97
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`define SGT 7'd98
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`define SGE 7'd99
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`define SLTU 7'd100
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`define SLEU 7'd101
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`define SGTU 7'd102
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`define SGEU 7'd103
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`define SEQ 7'd104
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`define SNE 7'd105
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`define BCD_ADD 7'd110
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`define BCD_SUB 7'd111
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`define SHFTI 7'd3
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`define SHLI 5'd0
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`define SHRUI 5'd1
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`define ROLI 5'd2
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`define SHRI 5'd3
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`define RORI 5'd4
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`define ROLAMI 5'd5
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`define BFINS 5'd8
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`define BFSET 5'd9
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`define BFCLR 5'd10
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`define BFCHG 5'd11
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`define ADDI 7'd4
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`define ADDUI 7'd5
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`define SUBI 7'd6
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`define SUBUI 7'd7
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`define CMPI 7'd8
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`define CMPUI 7'd9
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`define ANDI 7'd10
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`define ORI 7'd11
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`define XORI 7'd12
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`define MULUI 7'd13
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`define MULSI 7'd14
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`define DIVUI 7'd15
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`define DIVSI 7'd16
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`define TRAPcc 7'd17
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`define TEQ 5'd0
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`define TNE 5'd1
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`define TLT 5'd2
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`define TGE 5'd3
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`define TLE 5'd4
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`define TGT 5'd5
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`define TLTU 5'd6
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`define TGEU 5'd7
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`define TLEU 5'd8
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`define TGTU 5'd9
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`define TRAP 5'd10
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`define TRN 5'd11
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`define TRAPcci 7'd18
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`define TEQI 5'd0
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`define TNEI 5'd1
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`define TLTI 5'd2
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`define TGEI 5'd3
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`define TLEI 5'd4
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`define TGTI 5'd5
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`define TLTUI 5'd6
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`define TGEUI 5'd7
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`define TLEUI 5'd8
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`define TGTUI 5'd9
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`define TRAI 5'd10
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`define TRNI 5'd11
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// SETLO=20 to 23
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`define SETLO 7'b00101xx
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`define CALL 7'd24
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`define JMP 7'd25
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`define JAL 7'd26
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`define RET 7'd27
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// SETLO=28 to 31
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`define SETHI 7'b00111xx
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`define LB 7'd32
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`define LC 7'd33
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`define LH 7'd34
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`define LW 7'd35
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`define LP 7'd36
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`define LBU 7'd37
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`define LCU 7'd38
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`define LHU 7'd39
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`define LSH 7'd40
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`define LSW 7'd41
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`define LF 7'd42
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`define LFD 7'd43
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`define LFP 7'd44
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`define LFDP 7'd45
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`define LWR 7'd46
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`define LDONE 7'd47
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`define SB 7'd48
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`define SC 7'd49
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`define SH 7'd50
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`define SW 7'd51
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`define SP 7'd52
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`define MEMNDX 7'd53
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`define LBX 6'd0
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`define LCX 6'd1
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`define LHX 6'd2
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`define LWX 6'd3
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`define LPX 6'd4
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`define LBUX 6'd5
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`define LCUX 6'd6
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`define LHUX 6'd7
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`define LSHX 6'd8
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`define LSWX 6'd9
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`define LFX 6'd10
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`define LFDX 6'd11
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`define LFPX 6'd12
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`define LFDPX 6'd13
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`define LWRX 6'd14
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`define SBX 6'd16
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`define SCX 6'd17
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`define SHX 6'd18
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`define SWX 6'd19
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`define SPX 6'd20
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`define SSHX 6'd24
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`define SSWX 6'd25
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`define SFX 6'd26
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`define SFDX 6'd27
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`define SFPX 6'd28
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`define SFDPX 6'd29
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`define SWCX 6'd30
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`define INBX 6'd32
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`define INCX 6'd33
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`define INHX 6'd34
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`define INWX 6'd35
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`define INBUX 6'd36
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`define INCUX 6'd37
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`define INHUX 6'd38
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`define OUTBX 6'd40
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`define OUTCX 6'd41
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`define OUTHX 6'd42
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`define OUTWX 6'd43
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`define CACHEX 6'd44
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`define LEAX 6'd45
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`define LMX 6'd46
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`define SMX 6'd47
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`define SSH 7'd56
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`define SSW 7'd57
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`define SF 7'd58
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`define SFD 7'd59
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`define SFP 7'd60
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`define SFDP 7'd61
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`define SWC 7'd62
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|
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`define INB 7'd64
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`define INCH 7'd65
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`define INH 7'd66
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`define INW 7'd67
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`define INBU 7'd68
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`define INCU 7'd69
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`define INHU 7'd70
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`define OUTB 7'd72
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`define OUTC 7'd73
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`define OUTH 7'd74
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`define OUTW 7'd75
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`define CACHE 7'd76
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`define INVIL 5'd0
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`define INVIALL 5'd1
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`define LEA 7'd77
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`define LM 7'd78
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`define SM 7'd79
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|
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`define BLTI 7'd80
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`define BGEI 7'd81
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`define BLEI 7'd82
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`define BGTI 7'd83
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`define BLTUI 7'd84
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`define BGEUI 7'd85
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`define BLEUI 7'd86
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`define BGTUI 7'd87
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`define BEQI 7'd88
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`define BNEI 7'd89
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|
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`define BTRI 7'd94
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`define BLTRI 5'd0
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`define BGERI 5'd1
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`define BLERI 5'd2
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`define BGTRI 5'd3
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`define BLTURI 5'd4
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`define BGEURI 5'd5
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`define BLEURI 5'd6
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`define BGTURI 5'd7
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`define BEQRI 5'd8
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`define BNERI 5'd9
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`define BRARI 5'd10
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`define BRNRI 5'd11
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`define BANDRI 5'd12
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`define BORRI 5'd13
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`define BTRR 7'd95
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`define BLT 5'd0
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`define BGE 5'd1
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`define BLE 5'd2
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`define BGT 5'd3
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`define BLTU 5'd4
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`define BGEU 5'd5
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`define BLEU 5'd6
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`define BGTU 5'd7
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`define BEQ 5'd8
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`define BNE 5'd9
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`define BRA 5'd10
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`define BRN 5'd11
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`define BAND 5'd12
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`define BOR 5'd13
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`define BNR 5'd14
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`define LOOP 5'd15
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`define BLTR 5'd16
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`define BGER 5'd17
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`define BLER 5'd18
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`define BGTR 5'd19
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`define BLTUR 5'd20
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`define BGEUR 5'd21
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`define BLEUR 5'd22
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`define BGTUR 5'd23
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`define BEQR 5'd24
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`define BNER 5'd25
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`define BRAR 5'd26
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`define BRNR 5'd27
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|
|
|
|
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`define SLTI 7'd96
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`define SLEI 7'd97
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`define SGTI 7'd98
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`define SGEI 7'd99
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`define SLTUI 7'd100
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`define SLEUI 7'd101
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`define SGTUI 7'd102
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`define SGEUI 7'd103
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`define SEQI 7'd104
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`define SNEI 7'd105
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|
|
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`define FP 7'd108
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`define FDADD 6'd0
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`define FDSUB 6'd1
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`define FDMUL 6'd2
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`define FDDIV 6'd3
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`define FDCUN 6'd4
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`define FDI2F 6'd5
|
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`define FDF2I 6'd6
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`define FDF2D 6'd7
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`define FDD2F 6'd8
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`define FDCLT 6'b001100
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`define FDCEQ 6'b010100
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`define FDCLE 6'b011100
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`define FDCGT 6'b100100
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`define FDCNE 6'b101100
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`define FDCGE 6'b110100
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`define FPLOO 7'd109
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`define FPZL 7'd110
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`define NOPI 7'd111
|
|
|
|
`define IMM 3'd7
|
|
|
|
`define NOP_INSN 42'b1101111_000_00000000_00000000_00000000_00000000
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|
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, bte_o, cti_o, bl_o,
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, bte_o, cti_o, bl_o,
|
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
|
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
|
);
|
);
|
parameter IDLE = 5'd1;
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parameter IDLE = 5'd1;
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| Line 510... |
Line 117... |
reg [1:0] vtno; // vector table number
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reg [1:0] vtno; // vector table number
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reg [1:0] rm; // fp rounding mode
|
reg [1:0] rm; // fp rounding mode
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reg FXE; // fp exception enable
|
reg FXE; // fp exception enable
|
wire KernelMode;
|
wire KernelMode;
|
wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,vtno,10'b0};
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wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,vtno,10'b0};
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reg [41:0] dIR;
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reg [41:0] dIR,xIR,m1IR,m2IR,wIR;
|
reg [41:0] ndIR;
|
reg [41:0] ndIR;
|
wire [6:0] dOpcode = dIR[41:35];
|
wire [6:0] dOpcode = dIR[41:35];
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reg [41:0] xIR;
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reg [63:0] pc;
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reg [63:0] pc;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] dpc,m1pc,m2pc,wpc;
|
reg [63:0] dpc,m1pc,m2pc,wpc;
|
reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
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reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
|
reg [63:0] xpc;
|
reg [63:0] xpc;
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| Line 571... |
Line 177... |
integer n;
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integer n;
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reg [63:13] BadVAddr;
|
reg [63:13] BadVAddr;
|
reg [63:13] PageTableAddr;
|
reg [63:13] PageTableAddr;
|
reg [63:0] errorAddress;
|
reg [63:0] errorAddress;
|
|
|
|
wire [6:0] iFunc = insn[6:0];
|
|
wire [6:0] dFunc = dIR[6:0];
|
|
wire [5:0] dFunc6 = dIR[5:0];
|
|
wire [6:0] xFunc = xIR[6:0];
|
|
wire [5:0] xFunc6 = xIR[5:0];
|
|
wire [4:0] xFunc5 = xIR[4:0];
|
|
wire [6:0] iOpcode = insn[41:35];
|
|
wire [6:0] xOpcode = xIR[41:35];
|
|
reg [6:0] m1Opcode,m2Opcode,wOpcode;
|
|
reg [6:0] m1Func,m2Func,wFunc;
|
|
reg [63:0] m1Data,m2Data,wData,tData;
|
|
reg [63:0] m2Addr;
|
|
reg [63:0] tick;
|
|
reg [63:0] tba;
|
|
reg [63:0] exception_address,ipc;
|
|
reg [63:0] a,b,c,imm,m1b;
|
|
reg prev_ihit;
|
|
reg rsf;
|
|
reg [63:5] resv_address;
|
|
reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
|
|
reg xirqf;
|
|
reg [8:0] dextype,m1extype,m2extype,wextype,textype,exception_type;
|
|
reg [8:0] xextype;
|
|
reg wLdPC,m2LdPC;
|
|
wire advanceX_edge;
|
|
reg takb;
|
|
wire advanceX,advanceM1,advanceW;
|
|
reg m1IsLoad,m2IsLoad;
|
|
reg m1IsIO;
|
|
reg m1IsStore,m2IsStore,wIsStore;
|
|
|
function [63:0] fnIncPC;
|
function [63:0] fnIncPC;
|
input [63:0] fpc;
|
input [63:0] fpc;
|
begin
|
begin
|
case(fpc[3:2])
|
case(fpc[3:2])
|
2'd0: fnIncPC = {fpc[63:4],4'b0100};
|
2'd0: fnIncPC = {fpc[63:4],4'b0100};
|
| Line 590... |
Line 227... |
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// TLB
|
// TLB
|
// The TLB contains 64 entries, that are 8 way set associative.
|
// The TLB contains 64 entries, that are 8 way set associative.
|
// The TLB is dual ported and shared between the instruction and data streams.
|
// The TLB is dual ported and shared between the instruction and data streams.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
wire unmappedArea = pc[63:52]==12'hFFD || pc[63:52]==12'hFFE || pc[63:52]==12'hFFF;
|
|
wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF;
|
|
wire [63:0] ppc;
|
wire [63:0] ppc;
|
wire [63:0] pea;
|
wire [63:0] pea;
|
|
wire [63:0] tlbo;
|
`ifdef TLB
|
`ifdef TLB
|
reg [24:13] TLBPageMask;
|
wire [63:0] TLBVirtPage;
|
reg [63:13] TLBVirtPage;
|
wire wTlbp = advanceW && wOpcode==`MISC && wFunc==`TLBP;
|
reg [63:13] TLBPhysPage0;
|
wire wTlbrd = advanceW && wOpcode==`MISC && wFunc==`TLBR;
|
reg [63:13] TLBPhysPage1;
|
wire wTlbwr = advanceW && wOpcode==`MISC && wFunc==`TLBWR;
|
reg [7:0] TLBASID;
|
wire wTlbwi = advanceW && wOpcode==`MISC && wFunc==`TLBWI;
|
reg TLBG;
|
wire wMtspr = advanceW && wOpcode==`R && wFunc==`MTSPR;
|
reg TLBD;
|
wire xTlbrd = advanceX && xOpcode==`MISC && xFunc==`TLBR;
|
reg TLBValid;
|
wire xTlbwr = advanceX && xOpcode==`MISC && xFunc==`TLBWR;
|
reg [63:0] Index;
|
wire xTlbwi = advanceX && xOpcode==`MISC && xFunc==`TLBWI;
|
reg [2:0] Random;
|
wire ITLBMiss,DTLBMiss;
|
reg [2:0] Wired;
|
|
reg [15:0] IMatch,DMatch;
|
|
|
|
reg [3:0] m;
|
|
reg [5:0] i;
|
|
reg [24:13] ITLBPageMask [63:0];
|
|
reg [63:13] ITLBVirtPage [63:0];
|
|
reg [63:13] ITLBPhysPage0 [63:0];
|
|
reg [63:13] ITLBPhysPage1 [63:0];
|
|
reg [63:0] ITLBG;
|
|
reg [63:0] ITLBD;
|
|
reg [7:0] ITLBASID [63:0];
|
|
reg [15:0] ITLBValid;
|
|
initial begin
|
|
for (n = 0; n < 64; n = n + 1)
|
|
begin
|
|
ITLBPageMask[n] = 0;
|
|
ITLBVirtPage[n] = 0;
|
|
ITLBPhysPage0[n] = 0;
|
|
ITLBPhysPage1[n] = 0;
|
|
ITLBG[n] = 0;
|
|
ITLBASID[n] = 0;
|
|
ITLBValid[n] = 0;
|
|
end
|
|
end
|
|
always @*
|
|
for (n = 0; n < 8; n = n + 1)
|
|
IMatch[n] = ((pc[63:13]|ITLBPageMask[{n[2:0],pc[15:13]}])==(ITLBVirtPage[{n[2:0],pc[15:13]}]|ITLBPageMask[{n[2:0],pc[15:13]}])) &&
|
|
((ITLBASID[{n,pc[15:13]}]==ASID) || ITLBG[{n,pc[15:13]}]) &&
|
|
ITLBValid[{n,pc[15:13]}];
|
|
always @(IMatch)
|
|
if (IMatch[0]) m <= 4'd0;
|
|
else if (IMatch[1]) m <= 4'd1;
|
|
else if (IMatch[2]) m <= 4'd2;
|
|
else if (IMatch[3]) m <= 4'd3;
|
|
else if (IMatch[4]) m <= 4'd4;
|
|
else if (IMatch[5]) m <= 4'd5;
|
|
else if (IMatch[6]) m <= 4'd6;
|
|
else if (IMatch[7]) m <= 4'd7;
|
|
else m <= 4'd15;
|
|
|
|
wire ioddpage = |({ITLBPageMask[{m[2:0],pc[15:13]}]+19'd1,13'd0}&pc);
|
|
wire [63:13] IPFN = ioddpage ? ITLBPhysPage1[{m[2:0],pc[15:13]}] : ITLBPhysPage0[{m[2:0],pc[15:13]}];
|
|
|
|
wire ITLBMiss = !unmappedArea & m[3];
|
|
|
|
assign ppc[63:13] = unmappedArea ? pc[63:13] : m[3] ? `TLBMissPage: IPFN;
|
|
assign ppc[12:0] = pc[12:0];
|
|
|
|
reg [3:0] q;
|
|
always @(ea)
|
|
for (n = 0; n < 7; n = n + 1)
|
|
DMatch[n] = ((ea[63:13]|ITLBPageMask[{n,ea[15:13]}])==(ITLBVirtPage[{n,ea[15:13]}]|ITLBPageMask[{n,ea[15:13]}])) &&
|
|
((ITLBASID[{n,ea[15:13]}]==ASID) || ITLBG[{n,ea[15:13]}]) &&
|
|
ITLBValid[{n,ea[15:13]}];
|
|
always @(DMatch)
|
|
if (DMatch[0]) q <= 4'd0;
|
|
else if (DMatch[1]) q <= 4'd1;
|
|
else if (DMatch[2]) q <= 4'd2;
|
|
else if (DMatch[3]) q <= 4'd3;
|
|
else if (DMatch[4]) q <= 4'd4;
|
|
else if (DMatch[5]) q <= 4'd5;
|
|
else if (DMatch[6]) q <= 4'd6;
|
|
else if (DMatch[7]) q <= 4'd7;
|
|
else q <= 4'd15;
|
|
|
|
wire doddpage = |({ITLBPageMask[{q[2:0],ea[15:13]}]+19'd1,13'd0}&ea);
|
|
wire [63:13] DPFN = doddpage ? ITLBPhysPage1[{q[2:0],ea[15:13]}] : ITLBPhysPage0[{q[2:0],ea[15:13]}];
|
|
|
|
wire DTLBMiss = !unmappedDataArea & q[3];
|
Raptor64_TLB u22
|
|
(
|
|
.rst(rst_i),
|
|
.clk(clk),
|
|
.pc(pc),
|
|
.ea(ea),
|
|
.ppc(ppc),
|
|
.pea(pea),
|
|
.m1IsStore(advanceM1 && m1IsStore),
|
|
.ASID(ASID),
|
|
.wTlbp(wTlbp),
|
|
.wTlbrd(wTlbrd),
|
|
.wTlbwr(wTlbwr),
|
|
.wTlbwi(wTlbwi),
|
|
.xTlbrd(xTlbrd),
|
|
.xTlbwr(xTlbwr),
|
|
.xTlbwi(xTlbwi),
|
|
.wr(wMtspr),
|
|
.wregno(wIR[12:7]),
|
|
.dati(wData),
|
|
.xregno(xIR[12:7]),
|
|
.dato(tlbo),
|
|
.ITLBMiss(ITLBMiss),
|
|
.DTLBMiss(DTLBMiss),
|
|
.HTLBVirtPage(TLBVirtPage)
|
|
);
|
|
|
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[3] ? `TLBMissPage: DPFN;
|
|
assign pea[12:0] = ea[12:0];
|
|
`else
|
`else
|
assign ppc = pc;
|
assign ppc = pc;
|
assign pea = ea;
|
assign pea = ea;
|
`endif
|
`endif
|
wire m1UnmappedDataArea = pea[63:13]>=12'hFFD;
|
|
|
|
wire dram_bus = !pea[63];
|
wire dram_bus = !pea[63];
|
wire m2_dram_bus = !m2Addr[63];
|
wire m2_dram_bus = !m2Addr[63];
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
| Line 871... |
Line 459... |
reg [64:0] xData;
|
reg [64:0] xData;
|
wire xisCacheElement = (xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF) && dcache_on;
|
wire xisCacheElement = (xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF) && dcache_on;
|
reg m1IsCacheElement;
|
reg m1IsCacheElement;
|
|
|
reg nopI;
|
reg nopI;
|
wire [6:0] iFunc = insn[6:0];
|
|
wire [6:0] dFunc = dIR[6:0];
|
|
wire [5:0] dFunc6 = dIR[5:0];
|
|
wire [6:0] xFunc = xIR[6:0];
|
|
wire [5:0] xFunc6 = xIR[5:0];
|
|
wire [4:0] xFunc5 = xIR[4:0];
|
|
wire [6:0] iOpcode = insn[41:35];
|
|
wire [6:0] xOpcode = xIR[41:35];
|
|
reg [6:0] m1Opcode,m2Opcode,wOpcode;
|
|
reg [6:0] m1Func,m2Func;
|
|
reg [63:0] m1Data,m2Data,wData,tData;
|
|
reg [63:0] m2Addr;
|
|
reg [63:0] tick;
|
|
reg [63:0] tba;
|
|
reg [63:0] exception_address,ipc;
|
|
reg [63:0] a,b,c,imm,m1b;
|
|
reg prev_ihit;
|
|
reg rsf;
|
|
reg [63:5] resv_address;
|
|
reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
|
|
reg xirqf;
|
|
reg [8:0] dextype,m1extype,m2extype,wextype,textype,exception_type;
|
|
reg [8:0] xextype;
|
|
reg wLdPC,m2LdPC;
|
|
wire advanceX_edge;
|
|
reg takb;
|
|
|
|
|
|
|
|
wire [127:0] mult_out;
|
wire [127:0] mult_out;
|
wire [63:0] sqrt_out;
|
wire [63:0] sqrt_out;
|
| Line 1246... |
Line 808... |
predict_taken = insn[29];
|
predict_taken = insn[29];
|
default:
|
default:
|
predict_taken = 1'd0;
|
predict_taken = 1'd0;
|
endcase
|
endcase
|
`else
|
`else
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Branch history table.
|
// Branch history table.
|
// The history table is updated by the EX stage and read in
|
// The history table is updated by the EX stage and read in
|
// both the EX and IF stages.
|
// both the EX and IF stages.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
reg [2:0] gbl_branch_hist;
|
wire predict_taken;
|
reg [1:0] branch_history_table [255:0];
|
|
wire [7:0] bht_wa = {xpc[5:0],gbl_branch_hist[2:1]}; // write address
|
|
wire [7:0] bht_ra1 = {xpc[5:0],gbl_branch_hist[2:1]}; // read address (EX stage)
|
|
wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage)
|
|
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
|
|
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
|
|
wire predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
|
|
|
wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI ||
|
|
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
|
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
|
|
;
|
|
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
|
|
|
|
reg [1:0] xbits_new;
|
|
|
|
always @(takb or bht_xbits)
|
Raptor64_BranchHistory u6
|
if (takb) begin
|
(
|
if (bht_xbits != 2'd1)
|
.rst(rst_i),
|
xbits_new <= bht_xbits + 2'd1;
|
.clk(clk),
|
else
|
.advanceX(advanceX),
|
xbits_new <= bht_xbits;
|
.xIR(xIR),
|
end
|
.pc(pc),
|
else begin
|
.xpc(xpc),
|
if (bht_xbits != 2'd2)
|
.takb(takb),
|
xbits_new <= bht_xbits - 2'd1;
|
.predict_taken(predict_taken)
|
else
|
);
|
xbits_new <= bht_xbits;
|
|
end
|
|
|
|
// For simulation only, initialize the history table to zeros.
|
|
// In the real world we don't care.
|
|
initial begin
|
|
for (n = 0; n < 256; n = n + 1)
|
|
branch_history_table[n] = 0;
|
|
end
|
|
`endif
|
`endif
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Evaluate branch conditions.
|
// Evaluate branch conditions.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
| Line 1369... |
Line 908... |
`BLTUI: takb = ltui;
|
`BLTUI: takb = ltui;
|
`BLEUI: takb = ltui|eqi;
|
`BLEUI: takb = ltui|eqi;
|
`BGTUI: takb = !(ltui|eqi);
|
`BGTUI: takb = !(ltui|eqi);
|
`BGEUI: takb = !ltui;
|
`BGEUI: takb = !ltui;
|
`BTRI:
|
`BTRI:
|
case(xIR[24:18])
|
case(xIR[24:20])
|
`BRA: takb = 1'b1;
|
`BRA: takb = 1'b1;
|
`BRN: takb = 1'b0;
|
`BRN: takb = 1'b0;
|
`BEQ: takb = eqi;
|
`BEQ: takb = eqi;
|
`BNE: takb = !eqi;
|
`BNE: takb = !eqi;
|
`BLT: takb = lti;
|
`BLT: takb = lti;
|
| Line 1427... |
Line 966... |
cntlo64 u13 (.clk(clk), .i(a), .o(cntloo) );
|
cntlo64 u13 (.clk(clk), .i(a), .o(cntloo) );
|
|
|
reg [1:0] shftop;
|
reg [1:0] shftop;
|
wire [63:0] shfto;
|
wire [63:0] shfto;
|
reg [63:0] masko;
|
reg [63:0] masko;
|
//wire shl = (xOpcode==`RR && xFunc==`SHL) || (xOpcode==`SHFTI && xFunc==`SHLI);
|
reg [63:0] bfextd;
|
//wire shr = (xOpcode==`RR && xFunc==`SHR) || (xOpcode==`SHFTI && xFunc==`SHRI);
|
|
//wire shru = (xOpcode==`RR && xFunc==`SHRU) || (xOpcode==`SHFTI && xFunc==`SHRUI);
|
|
//wire rol = (xOpcode==`RR && xFunc==`ROL) || (xOpcode==`SHFTI && xFunc==`ROLI);
|
|
//wire ror = (xOpcode==`RR && xFunc==`ROR) || (xOpcode==`SHFTI && xFunc==`RORI);
|
|
//wire rolam = (xOpcode==`RR && xFunc==`ROLAM) || (xOpcode==`SHFTI && xFunc==`ROLAMI);
|
|
//
|
|
//always @(shl,shr,shru,rol,ror,rolam)
|
|
// if (shl) shftop = 2'b00;
|
|
// else if (rol | ror | rolam) shftop = 2'b01;
|
|
// else if (shru) shftop = 2'b10;
|
|
// else if (shr) shftop = 2'b11;
|
|
// else shftop = 2'b01;
|
|
|
|
wire [127:0] shlxo = {64'd0,a} << b[5:0];
|
wire [127:0] shlxo = {64'd0,a} << b[5:0];
|
wire [127:0] shruxo = {a,64'd0} >> b[5:0];
|
wire [127:0] shruxo = {a,64'd0} >> b[5:0];
|
wire [63:0] shlo = shlxo[63:0];
|
wire [63:0] shlo = shlxo[63:0];
|
wire [63:0] shruo = shruxo[127:64];
|
wire [63:0] shruo = shruxo[127:64];
|
wire [63:0] rolo = {shlo[127:64]|shlo[63:0]};
|
wire [63:0] rolo = {shlxo[127:64]|shlxo[63:0]};
|
wire [63:0] roro = {shruo[127:64]|shruo[63:0]};
|
wire [63:0] roro = {shruxo[127:64]|shruxo[63:0]};
|
wire [63:0] shro = ~(~a >> b[5:0]);
|
wire [63:0] shro = ~(~a >> b[5:0]);
|
// generate mask
|
// generate mask
|
wire [5:0] mb = xIR[12:7];
|
wire [5:0] mb = xIR[12:7];
|
wire [5:0] me = xIR[18:13];
|
wire [5:0] me = xIR[18:13];
|
integer nn;
|
integer nn;
|
always @(mb or me or nn)
|
always @(mb or me or nn)
|
for (nn = 0; nn < 64; nn = nn + 1)
|
for (nn = 0; nn < 64; nn = nn + 1)
|
masko[nn] <= (nn >= mb) ^ (nn <= me) ^ (me >= mb);
|
masko[nn] <= (nn >= mb) ^ (nn <= me) ^ (me >= mb);
|
/*
|
|
shiftAndMask #(64) u15
|
|
(
|
|
.op(shftop),
|
|
.oz(1'b0), // zero the output
|
|
.a(a),
|
|
.b(b[5:0]),
|
|
.mb(xIR[12:7]),
|
|
.me(xIR[18:13]),
|
|
.o(shfto),
|
|
.mo(masko)
|
|
);
|
|
|
|
*/
|
|
always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or
|
always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or
|
sqrt_out or cntlzo or cntloo or tick or ipc or tba or AXC or
|
sqrt_out or cntlzo or cntloo or tick or ipc or tba or AXC or
|
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut or
|
`ifdef TLB
|
`ifdef TLB
|
or Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
PageTableAddr or BadVAddr or ASID or tlbo or
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
|
`endif
|
`endif
|
or ASID or EPC or mutex_gate or IPC or CauseCode or TBA or xAXC or nonICacheSeg or rm or
|
ASID or EPC or mutex_gate or IPC or CauseCode or TBA or xAXC or nonICacheSeg or rm or
|
rando
|
rando
|
)
|
)
|
casex(xOpcode)
|
casex(xOpcode)
|
`R:
|
`R:
|
casex(xFunc)
|
casex(xFunc)
|
| Line 1513... |
Line 1025... |
;
|
;
|
`SEXT8: xData = {{56{a[7]}},a[7:0]};
|
`SEXT8: xData = {{56{a[7]}},a[7:0]};
|
`SEXT16: xData = {{48{a[15]}},a[15:0]};
|
`SEXT16: xData = {{48{a[15]}},a[15:0]};
|
`SEXT32: xData = {{32{a[31]}},a[31:0]};
|
`SEXT32: xData = {{32{a[31]}},a[31:0]};
|
|
|
|
`MTSPR: xData = a;
|
`MFSPR:
|
`MFSPR:
|
case(xIR[12:7])
|
case(xIR[12:7])
|
`ifdef TLB
|
`ifdef TLB
|
`Wired: xData = Wired;
|
`TLBWired: xData = tlbo;
|
`TLBIndex: xData = Index;
|
`TLBIndex: xData = tlbo;
|
`TLBRandom: xData = Random;
|
`TLBRandom: xData = tlbo;
|
`TLBPhysPage0: xData = {TLBPhysPage0,13'd0};
|
`TLBPhysPage0: xData = tlbo;
|
`TLBPhysPage1: xData = {TLBPhysPage1,13'd0};
|
`TLBPhysPage1: xData = tlbo;
|
`TLBVirtPage: xData = {TLBVirtPage,13'd0};
|
`TLBVirtPage: xData = tlbo;
|
`TLBPageMask: xData = {TLBPageMask,13'd0};
|
`TLBPageMask: xData = tlbo;
|
`TLBASID: begin
|
`TLBASID: begin
|
xData = 65'd0;
|
xData = 65'd0;
|
xData[0] = TLBValid;
|
xData[0] = tlbo[0];
|
xData[1] = TLBD;
|
xData[1] = tlbo[1];
|
xData[2] = TLBG;
|
xData[2] = tlbo[2];
|
xData[15:8] = TLBASID;
|
xData[15:8] = tlbo[15:8];
|
end
|
end
|
`PageTableAddr: xData = {PageTableAddr,13'd0};
|
`PageTableAddr: xData = {PageTableAddr,13'd0};
|
`BadVAddr: xData = {BadVAddr,13'd0};
|
`BadVAddr: xData = {BadVAddr,13'd0};
|
`endif
|
`endif
|
`ASID: xData = ASID;
|
`ASID: xData = ASID;
|
| Line 1543... |
Line 1056... |
`TBA: xData = TBA;
|
`TBA: xData = TBA;
|
`AXC: xData = xAXC;
|
`AXC: xData = xAXC;
|
`NON_ICACHE_SEG: xData = nonICacheSeg;
|
`NON_ICACHE_SEG: xData = nonICacheSeg;
|
`FPCR: xData = FPC;
|
`FPCR: xData = FPC;
|
`RAND: xData = rando;
|
`RAND: xData = rando;
|
`SRANDZ: xData = {m_z2,m_z1};
|
`SRAND1: xData = {m_z2,m_z1};
|
`SRANDW: xData = {m_w2,m_w1};
|
`SRAND2: xData = {m_w2,m_w1};
|
`INSNKEY: xData = insnkey;
|
`INSNKEY: xData = insnkey;
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
`OMG: xData = mutex_gate[a[5:0]];
|
`OMG: xData = mutex_gate[a[5:0]];
|
`CMG: xData = mutex_gate[a[5:0]];
|
`CMG: xData = mutex_gate[a[5:0]];
|
| Line 1614... |
Line 1127... |
`ROLAMI: xData = rolo & masko;
|
`ROLAMI: xData = rolo & masko;
|
`BFINS: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? rolo[n] : b[n]; xData[64] = 1'b0; end
|
`BFINS: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? rolo[n] : b[n]; xData[64] = 1'b0; end
|
`BFSET: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
|
`BFSET: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
|
`BFCLR: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
|
`BFCLR: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
|
`BFCHG: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
|
`BFCHG: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
|
|
`BFEXT: begin for (n = 0; n < 64; n = n + 1) bfextd[n] = masko[n] ? b[n] : 1'b0; xData = bfextd >> mb; end
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
`BTRR:
|
`BTRR:
|
case(xFunc5)
|
case(xFunc5)
|
`LOOP: xData = b - 64'd1;
|
`LOOP: xData = b - 64'd1;
|
| Line 1656... |
Line 1170... |
xData = a + imm;
|
xData = a + imm;
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SP,`SFP,`SFDP:
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SP,`SFP,`SFDP:
|
xData = a + imm;
|
xData = a + imm;
|
`MEMNDX:
|
`MEMNDX:
|
xData = a + b + imm;
|
xData = a + b + imm;
|
`SM: xData = a + {popcnt36(xIR[31:0]),3'b000};
|
`SM: xData = a + {popcnt36(xIR[31:0]),3'b000}-64'd8;
|
`LM: xData = a + {popcnt36(xIR[31:0]),3'b000};
|
`LM: xData = a + {popcnt36(xIR[31:0]),3'b000}-64'd8;
|
`TRAPcc: xData = fnIncPC(xpc);
|
`TRAPcc: xData = fnIncPC(xpc);
|
`TRAPcci: xData = fnIncPC(xpc);
|
`TRAPcci: xData = fnIncPC(xpc);
|
`CALL: xData = fnIncPC(xpc);
|
`CALL: xData = fnIncPC(xpc);
|
`JAL: xData = xpc + {xIR[29:25],2'b00};
|
`JAL: xData = xpc + {xIR[29:25],2'b00};
|
`RET: xData = a + imm;
|
`RET: xData = a + imm;
|
| Line 1747... |
Line 1261... |
wire xIsIO =
|
wire xIsIO =
|
xIsIn ||
|
xIsIn ||
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB
|
;
|
;
|
|
|
reg m1IsLoad,m2IsLoad;
|
|
reg m1IsIO;
|
|
reg m1IsStore,m2IsStore,wIsStore;
|
|
|
|
|
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
wire xIsFP = xOpcode==`FP;
|
wire xIsFP = xOpcode==`FP;
|
wire xneedBus = xIsIO;
|
wire xneedBus = xIsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
| Line 1771... |
Line 1281... |
( m1IsLoad & m1IsCacheElement & (m2IsStore|wIsStore)) // wait for a preceding store to complete
|
( m1IsLoad & m1IsCacheElement & (m2IsStore|wIsStore)) // wait for a preceding store to complete
|
;
|
;
|
wire StallM2 = icaccess|dcaccess;
|
wire StallM2 = icaccess|dcaccess;
|
|
|
wire advanceT = !resetA;
|
wire advanceT = !resetA;
|
wire advanceW = advanceT;
|
assign advanceW = advanceT;
|
wire advanceM2 = advanceW &&
|
wire advanceM2 = advanceW &&
|
((m2IsLoad || m2IsStore) ? (ack_i|err_i) : 1'b1) &&
|
((m2IsLoad || m2IsStore) ? (ack_i|err_i) : 1'b1) &&
|
!StallM2
|
!StallM2
|
;
|
;
|
wire advanceM1 = advanceM2 &
|
assign advanceM1 = advanceM2 &
|
(m1IsIO ? (ack_i|err_i) : 1'b1) &
|
(m1IsIO ? (ack_i|err_i) : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
!StallM1
|
!StallM1
|
;
|
;
|
wire advanceX = advanceM1 & (
|
assign advanceX = advanceM1 & (
|
xIsSqrt ? sqrt_done :
|
xIsSqrt ? sqrt_done :
|
xIsMult ? mult_done :
|
xIsMult ? mult_done :
|
xIsDiv ? div_done :
|
xIsDiv ? div_done :
|
xIsFPLoo ? fpLooDone :
|
xIsFPLoo ? fpLooDone :
|
xIsFP ? fltdone :
|
xIsFP ? fltdone :
|
| Line 1895... |
Line 1405... |
else
|
else
|
ndIR[31] <= 1'b0;
|
ndIR[31] <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
|
reg cyc1;
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Register file.
|
// Register file.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
|
|
syncRam512x64_1rw3r u5
|
wire [63:0] nxt_a, nxt_b, nxt_c;
|
|
|
|
Raptor64_regfile u5
|
(
|
(
|
.wrst(1'b0),
|
.clk(clk),
|
.wclk(clk),
|
.advanceR(advanceR),
|
.wce(advanceW),
|
.advanceW(advanceW),
|
.we(1'b1),
|
.dRa(dRa),
|
.wadr(wRt),
|
.dRb(dRb),
|
.i(wData),
|
.dRc(dRc),
|
.wo(),
|
.dpc(dpc),
|
|
.xRt(xRt),
|
.rrsta(1'b0),
|
.m1Rt(m1Rt),
|
.rclka(~clk),
|
.m2Rt(m2Rt),
|
.rcea(advanceR),
|
.wRt(wRt),
|
.radra(dRa),
|
.tRt(tRt),
|
.roa(rfoa),
|
.xData(xData[63:0]),
|
|
.m1Data(m1Data),
|
.rrstb(1'b0),
|
.m2Data(m2Data),
|
.rclkb(~clk),
|
.wData(wData),
|
.rceb(advanceR),
|
.tData(tData),
|
.radrb(dRb),
|
.nxt_a(nxt_a),
|
.rob(rfob),
|
.nxt_b(nxt_b),
|
|
.nxt_c(nxt_c)
|
.rrstc(1'b0),
|
|
.rclkc(~clk),
|
|
.rcec(advanceR),
|
|
.radrc(dRc),
|
|
.roc(rfoc)
|
|
);
|
);
|
|
|
|
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
|
reg cyc1;
|
|
|
|
reg [63:0] nxt_a;
|
|
always @(dRa or xData or m1Data or m2Data or wData or tData or rfoa)
|
|
casex(dRa)
|
|
9'bxxxx00000: nxt_a <= 64'd0;
|
|
xRt: nxt_a <= xData;
|
|
m1Rt: nxt_a <= m1Data;
|
|
m2Rt: nxt_a <= m2Data;
|
|
wRt: nxt_a <= wData;
|
|
tRt: nxt_a <= tData;
|
|
default: nxt_a <= rfoa;
|
|
endcase
|
|
|
|
reg [63:0] nxt_b;
|
|
always @(dRb or xData or m1Data or m2Data or wData or tData or rfob)
|
|
casex(dRb)
|
|
9'bxxxx00000: nxt_b <= 64'd0;
|
|
xRt: nxt_b <= xData;
|
|
m1Rt: nxt_b <= m1Data;
|
|
m2Rt: nxt_b <= m2Data;
|
|
wRt: nxt_b <= wData;
|
|
tRt: nxt_b <= tData;
|
|
default: nxt_b <= rfob;
|
|
endcase
|
|
|
|
reg [63:0] nxt_c;
|
|
always @(dRc or xData or m1Data or m2Data or wData or tData or rfoc)
|
|
casex(dRc)
|
|
9'bxxxx00000: nxt_c <= 64'd0;
|
|
xRt: nxt_c <= xData;
|
|
m1Rt: nxt_c <= m1Data;
|
|
m2Rt: nxt_c <= m2Data;
|
|
wRt: nxt_c <= wData;
|
|
tRt: nxt_c <= tData;
|
|
default: nxt_c <= rfoc;
|
|
endcase
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst_i) begin
|
if (rst_i) begin
|
bte_o <= 2'b00;
|
bte_o <= 2'b00;
|
cti_o <= 3'b000;
|
cti_o <= 3'b000;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
| Line 2038... |
Line 1508... |
a <= 64'd0;
|
a <= 64'd0;
|
b <= 64'd0;
|
b <= 64'd0;
|
imm <= 64'd0;
|
imm <= 64'd0;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
`ifdef TLB
|
|
Random <= 4'hF;
|
|
Wired <= 4'd0;
|
|
`endif
|
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
StatusHWI <= 1'b0;
|
StatusHWI <= 1'b0;
|
resetA <= 1'b1;
|
resetA <= 1'b1;
|
mutex_gate <= 64'h0;
|
mutex_gate <= 64'h0;
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
|
gbl_branch_hist <= 3'b000;
|
|
`endif
|
|
dcache_on <= 1'b0;
|
dcache_on <= 1'b0;
|
ICacheOn <= 1'b0;
|
ICacheOn <= 1'b0;
|
ibuftag0 <= 64'h0;
|
ibuftag0 <= 64'h0;
|
ibuftag1 <= 64'h0;
|
ibuftag1 <= 64'h0;
|
m1IsCacheElement <= 1'b0;
|
m1IsCacheElement <= 1'b0;
|
| Line 2083... |
Line 1546... |
dtinit <= 1'b0;
|
dtinit <= 1'b0;
|
resetA <= 1'b0;
|
resetA <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
`ifdef TLB
|
|
if (Random==Wired)
|
|
Random <= 3'd7;
|
|
else
|
|
Random <= Random - 3'd1;
|
|
`endif
|
|
|
|
tick <= tick + 64'd1;
|
tick <= tick + 64'd1;
|
|
|
prev_nmi <= nmi_i;
|
prev_nmi <= nmi_i;
|
if (!prev_nmi & nmi_i)
|
if (!prev_nmi & nmi_i)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
| Line 2173... |
Line 1629... |
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// MEMORY:
|
// MEMORY:
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceM2) begin
|
if (advanceM2) begin
|
wIsStore <= m2IsStore;
|
wIsStore <= m2IsStore;
|
|
wIR <= m2IR;
|
wOpcode <= m2Opcode;
|
wOpcode <= m2Opcode;
|
|
wFunc <= m2Func;
|
wData <= m2Data;
|
wData <= m2Data;
|
whwxtype <= m2hwxtype;
|
whwxtype <= m2hwxtype;
|
wextype <= (m2IsLoad|m2IsStore)&err_i ? `EX_DBERR : m2extype;
|
wextype <= (m2IsLoad|m2IsStore)&err_i ? `EX_DBERR : m2extype;
|
if (m2extype==`EX_IRQ)
|
if (m2extype==`EX_IRQ)
|
$display("m2extype=IRQ");
|
$display("m2extype=IRQ");
|
| Line 2315... |
Line 1773... |
// finished in this stage. We switch the opcode to 'NOPI'
|
// finished in this stage. We switch the opcode to 'NOPI'
|
// to cause the pipeline to advance as if a NOPs were
|
// to cause the pipeline to advance as if a NOPs were
|
// present.
|
// present.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceM1) begin
|
if (advanceM1) begin
|
|
m2IR <= m1IR;
|
m2Opcode <= m1Opcode;
|
m2Opcode <= m1Opcode;
|
m2Func <= m1Func;
|
m2Func <= m1Func;
|
m2IsLoad <= m1IsLoad;
|
m2IsLoad <= m1IsLoad;
|
m2IsStore <= m1IsStore;
|
m2IsStore <= m1IsStore;
|
m2IsCnt <= m1IsCnt;
|
m2IsCnt <= m1IsCnt;
|
| Line 2369... |
Line 1828... |
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2Data <= {cdat[63:2],2'b00};
|
m2Data <= {cdat[63:2],2'b00};
|
end
|
end
|
end
|
end
|
`ifdef TLB
|
|
`TLBP:
|
|
begin
|
|
Index[63] <= ~|DMatch;
|
|
end
|
|
`TLBR:
|
|
begin
|
|
TLBPageMask <= ITLBPageMask[i];
|
|
TLBVirtPage <= ITLBVirtPage[i];
|
|
TLBPhysPage0 <= ITLBPhysPage0[i];
|
|
TLBPhysPage1 <= ITLBPhysPage1[i];
|
|
TLBASID <= ITLBASID[i];
|
|
TLBG <= ITLBG[i];
|
|
TLBD <= ITLBD[i];
|
|
TLBValid <= ITLBValid[i];
|
|
end
|
|
`TLBWI,`TLBWR:
|
|
begin
|
|
ITLBValid[i] <= TLBValid;
|
|
ITLBVirtPage[i] <= TLBVirtPage;
|
|
ITLBPhysPage0[i] <= TLBPhysPage0;
|
|
ITLBPhysPage1[i] <= TLBPhysPage1;
|
|
ITLBPageMask[i] <= TLBPageMask;
|
|
ITLBASID[i] <= TLBASID;
|
|
ITLBD[i] <= TLBD;
|
|
ITLBG[i] <= TLBG;
|
|
end
|
|
`endif
|
|
endcase
|
endcase
|
`INW:
|
`INW:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
| Line 2678... |
Line 2109... |
`SW,`SM,`SFD,`SSW,`SP,`SFDP:
|
`SW,`SM,`SFD,`SSW,`SP,`SFDP:
|
begin
|
begin
|
$display("SW/SM");
|
$display("SW/SM");
|
m2Addr <= {pea[63:3],3'b000};
|
m2Addr <= {pea[63:3],3'b000};
|
wrhit <= dhit;
|
wrhit <= dhit;
|
`ifdef TLB
|
|
if (!m1UnmappedDataArea & !q[3])
|
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
`endif
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
| Line 2698... |
Line 2125... |
|
|
`SH,`SF,`SSH,`SFP:
|
`SH,`SF,`SSH,`SFP:
|
begin
|
begin
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
`ifdef TLB
|
|
if (!m1UnmappedDataArea & !q[3])
|
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
`endif
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
| Line 2719... |
Line 2142... |
`SC:
|
`SC:
|
begin
|
begin
|
$display("Storing char to %h, ea=%h",pea,ea);
|
$display("Storing char to %h, ea=%h",pea,ea);
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
`ifdef TLB
|
|
if (!m1UnmappedDataArea & !q[3])
|
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
`endif
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
| Line 2748... |
Line 2167... |
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
`ifdef ADDRESS_RESERVATION
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
`endif
|
`endif
|
`ifdef TLB
|
|
if (!m1UnmappedDataArea & !q[3])
|
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
|
`endif
|
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(pea[2:0])
|
case(pea[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
| Line 2774... |
Line 2189... |
`ifdef ADDRESS_RESERVATION
|
`ifdef ADDRESS_RESERVATION
|
`SWC:
|
`SWC:
|
begin
|
begin
|
rsf <= 1'b0;
|
rsf <= 1'b0;
|
if (resv_address==pea[63:5]) begin
|
if (resv_address==pea[63:5]) begin
|
`ifdef TLB
|
|
if (!m1UnmappedDataArea & !q[3])
|
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
|
`endif
|
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:3],3'b00};
|
m2Addr <= {pea[63:3],3'b00};
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
| Line 2803... |
Line 2214... |
// EXECUTE:
|
// EXECUTE:
|
// - perform datapath operation
|
// - perform datapath operation
|
// - perform virtual to physical address translation.
|
// - perform virtual to physical address translation.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceX) begin
|
if (advanceX) begin
|
|
m1IR <= xIR;
|
m1hwxtype <= xhwxtype;
|
m1hwxtype <= xhwxtype;
|
m1Fip <= xFip;
|
m1Fip <= xFip;
|
m1extype <= xextype;
|
m1extype <= xextype;
|
if (xextype==`EX_IRQ)
|
if (xextype==`EX_IRQ)
|
$display("xextype=IRQ");
|
$display("xextype=IRQ");
|
| Line 2866... |
Line 2278... |
begin
|
begin
|
ea <= {TBA[63:12],xIR[15:7],3'b000};
|
ea <= {TBA[63:12],xIR[15:7],3'b000};
|
end
|
end
|
`ifdef TLB
|
`ifdef TLB
|
`TLBP: ea <= TLBVirtPage;
|
`TLBP: ea <= TLBVirtPage;
|
`TLBR,`TLBWI:
|
|
begin
|
|
i <= {Index[2:0],TLBVirtPage[15:13]};
|
|
end
|
|
`TLBWR:
|
|
begin
|
|
i <= {Random,TLBVirtPage[15:13]};
|
|
end
|
|
`endif
|
`endif
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`R:
|
`R:
|
case(xFunc)
|
case(xFunc)
|
`MTSPR:
|
`MTSPR:
|
case(xIR[12:7])
|
case(xIR[12:7])
|
`ifdef TLB
|
`ifdef TLB
|
`Wired: Wired <= a[2:0];
|
|
`TLBIndex: Index <= a[2:0];
|
|
`TLBVirtPage: TLBVirtPage <= a[63:13];
|
|
`TLBPhysPage0: TLBPhysPage0 <= a[63:13];
|
|
`TLBPhysPage1: TLBPhysPage1 <= a[63:13];
|
|
`TLBPageMask: TLBPageMask <= a[24:13];
|
|
`TLBASID: begin
|
|
TLBValid <= a[0];
|
|
TLBD <= a[1];
|
|
TLBG <= a[2];
|
|
TLBASID <= a[15:8];
|
|
end
|
|
`PageTableAddr: PageTableAddr <= a[63:13];
|
`PageTableAddr: PageTableAddr <= a[63:13];
|
`BadVAddr: BadVAddr <= a[63:13];
|
`BadVAddr: BadVAddr <= a[63:13];
|
`endif
|
`endif
|
`ASID: ASID <= a[7:0];
|
`ASID: ASID <= a[7:0];
|
`EPC: EPC <= a;
|
`EPC: EPC <= a;
|
`TBA: TBA <= {a[63:12],12'h000};
|
`TBA: TBA <= {a[63:12],12'h000};
|
`AXC: AXC <= a[3:0];
|
`AXC: AXC <= a[3:0];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
`FPCR: rm <= a[31:30];
|
`FPCR: rm <= a[31:30];
|
`IPC: IPC <= a;
|
`IPC: IPC <= a;
|
`SRANDZ: begin
|
`SRAND1: begin
|
m_z1 <= a[31:0];
|
m_z1 <= a[31:0];
|
m_z2 <= a[63:32];
|
m_z2 <= a[63:32];
|
end
|
end
|
`SRANDW: begin
|
`SRAND2: begin
|
m_w1 <= a[31:0];
|
m_w1 <= a[31:0];
|
m_w2 <= a[63:32];
|
m_w2 <= a[63:32];
|
end
|
end
|
`INSNKEY: insnkey <= a[41:0];
|
`INSNKEY: insnkey <= a[41:0];
|
default: ;
|
default: ;
|
| Line 3101... |
Line 2493... |
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
|
// Update the branch history
|
|
if (isxBranch) begin
|
|
gbl_branch_hist <= {gbl_branch_hist,takb};
|
|
branch_history_table[bht_wa] <= xbits_new;
|
|
end
|
|
`endif
|
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// RFETCH:
|
// RFETCH:
|
// Register fetch stage
|
// Register fetch stage
|
| Line 3372... |
Line 2757... |
if ((iOpcode==`SP || iOpcode==`LP || iOpcode==`SFP || iOpcode==`LFP || iOpcode==`SFDP || iOpcode==`LFDP) && !insn[25])
|
if ((iOpcode==`SP || iOpcode==`LP || iOpcode==`SFP || iOpcode==`LFP || iOpcode==`SFDP || iOpcode==`LFDP) && !insn[25])
|
;
|
;
|
else if ((iOpcode==`LM || iOpcode==`SM) && insn[31:0]!=32'd0)
|
else if ((iOpcode==`LM || iOpcode==`SM) && insn[31:0]!=32'd0)
|
;
|
;
|
else begin
|
else begin
|
if (pc!=64'd3)
|
if (pc!=64'hC)
|
pc <= fnIncPC(pc);
|
pc <= fnIncPC(pc);
|
end
|
end
|
case(iOpcode)
|
case(iOpcode)
|
`MISC:
|
`MISC:
|
case(iFunc)
|
case(iFunc)
|
| Line 3472... |
Line 2857... |
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
`SYSJMP:
|
`SYSJMP:
|
begin
|
begin
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
pc <= 64'd3;
|
pc <= 64'hC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
`SYSCALL:
|
`SYSCALL:
|
begin
|
begin
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= fnIncPC(xpc);
|
EPC <= fnIncPC(xpc);
|
pc <= 64'd3;
|
pc <= 64'hC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 3645... |
Line 3030... |
`TRAPcc,`TRAPcci:
|
`TRAPcc,`TRAPcci:
|
if (takb) begin
|
if (takb) begin
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
CauseCode <= `EX_TRAP;
|
CauseCode <= `EX_TRAP;
|
xextype <= `EX_TRAP;
|
xextype <= `EX_TRAP;
|
pc <= 64'd3;
|
pc <= 64'hC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 3660... |
Line 3045... |
if (dbz_error) begin
|
if (dbz_error) begin
|
$display("Divide by zero error");
|
$display("Divide by zero error");
|
CauseCode <= `EX_DBZ;
|
CauseCode <= `EX_DBZ;
|
xextype <= `EX_DBZ;
|
xextype <= `EX_DBZ;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
pc <= 64'd3;
|
pc <= 64'hC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 3672... |
Line 3057... |
else if (ovr_error) begin
|
else if (ovr_error) begin
|
$display("Overflow error");
|
$display("Overflow error");
|
CauseCode <= `EX_OFL;
|
CauseCode <= `EX_OFL;
|
xextype <= `EX_OFL;
|
xextype <= `EX_OFL;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
pc <= 64'd3;
|
pc <= 64'hC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 3684... |
Line 3069... |
else if (priv_violation) begin
|
else if (priv_violation) begin
|
$display("Priviledge violation");
|
$display("Priviledge violation");
|
CauseCode <= `EX_PRIV;
|
CauseCode <= `EX_PRIV;
|
xextype <= `EX_PRIV;
|
xextype <= `EX_PRIV;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
pc <= 64'd3;
|
pc <= 64'hC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 3753... |
Line 3138... |
end
|
end
|
`EX_NMI,`EX_IRQ,`EX_DBERR:
|
`EX_NMI,`EX_IRQ,`EX_DBERR:
|
begin
|
begin
|
$display("Stuffing SYSJMP");
|
$display("Stuffing SYSJMP");
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
pc <= 64'd3;
|
pc <= 64'hC;
|
case(1'b1)
|
case(1'b1)
|
wpcv: IPC <= wpc;
|
wpcv: IPC <= wpc;
|
m2pcv: IPC <= m2pc;
|
m2pcv: IPC <= m2pc;
|
m1pcv: IPC <= m1pc;
|
m1pcv: IPC <= m1pc;
|
xpcv: IPC <= xpc;
|
xpcv: IPC <= xpc;
|
| Line 3766... |
Line 3151... |
endcase
|
endcase
|
end
|
end
|
`EX_OFL,`EX_DBZ,`EX_PRIV,`EX_TRAP:
|
`EX_OFL,`EX_DBZ,`EX_PRIV,`EX_TRAP:
|
begin
|
begin
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
pc <= 64'd3;
|
pc <= 64'hC;
|
EPC <= fnIncPC(wpc);
|
EPC <= fnIncPC(wpc);
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
pc <= 64'd3;
|
pc <= 64'hC;
|
EPC <= fnIncPC(wpc);
|
EPC <= fnIncPC(wpc);
|
end
|
end
|
endcase
|
endcase
|
if (wLdPC) begin
|
if (wLdPC) begin
|
$display("Loading PC");
|
$display("Loading PC");
|
