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`timescale 1ns / 1ps
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//=============================================================================
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//=============================================================================
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// (C) 2005-2012 Robert Finch
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// (C) 2005-2012 Robert Finch
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// All rights reserved.
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// All rights reserved.
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// robfinch@Opencores.org
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// robfinch@Opencores.org
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//
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//
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input cyc_i, // cycle valid
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input cyc_i, // cycle valid
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input stb_i, // strobe
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input stb_i, // strobe
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output ack_o, // transfer acknowledge
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output ack_o, // transfer acknowledge
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input we_i, // write
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input we_i, // write
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input [1:0] sel_i, // byte select
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input [1:0] sel_i, // byte select
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input [63:0] adr_i, // address
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input [23:0] adr_i, // address
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input [15:0] dat_i,
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input [15:0] dat_i,
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output reg [15:0] dat_o,
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output reg [15:0] dat_o,
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output vol_o, // volatile register selected
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output vol_o, // volatile register selected
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input i1, i2, i3, i4, i5, i6, i7,
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input i1, i2, i3, i4, i5, i6, i7,
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i8, i9, i10, i11, i12, i13, i14, i15,
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i8, i9, i10, i11, i12, i13, i14, i15,
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);
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);
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reg [15:0] ie; // interrupt enable register
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reg [15:0] ie; // interrupt enable register
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reg ack1;
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reg ack1;
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wire cs = cyc_i && stb_i && adr_i[63:4]==60'hFFFF_FFFF_FFDC_0FF;
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wire cs = cyc_i && stb_i && adr_i[23:4]==20'hDC_0FF;
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assign vol_o = cs;
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assign vol_o = cs;
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always @(posedge clk_i)
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always @(posedge clk_i)
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ack1 <= cs & !ack_o;
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ack1 <= cs;
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assign ack_o = ack1 && cs;
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assign ack_o = cs ? (we_i ? 1'b1 : ack1) : 1'b0;
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// write registers
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// write registers
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i)
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if (rst_i)
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ie <= 16'h0;
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ie <= 16'h0;
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