OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp/] [arithblock.vhd] - Diff between revs 152 and 153

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 152 Rev 153
Line 109... Line 109...
        );
        );
        --!TBXINSTANCESTART
        --!TBXINSTANCESTART
        mul_i_0 : fmul32
        mul_i_0 : fmul32
        port map (
        port map (
                clk => clk,
                clk => clk,
                dpc => dpc,
                a32 => f( 31    downto 0),
                a32 => a( 95    downto 64),
                b32 => f( 63    downto 32),
                b32 => a( 127   downto 96),
                p32 => p( 31    downto 0)
                c32 => s( 63    downto 32)
 
        );
        );
        --!TBXINSTANCESTART
        --!TBXINSTANCESTART
        mul_i_1 : fmul32
        mul_i_1 : fmul32
        port map (
        port map (
                clk => clk,
                clk => clk,
                dpc => dpc,
                a32 => f( 95    downto 64),
                a32 => a( 159   downto 128),
                b32 => f( 127   downto 96),
                b32 => a( 191   downto 160),
                p32 => p( 63    downto 32)
                c32 => s( 95    downto 64)
 
        );
        );
        --!TBXINSTANCESTART
        --!TBXINSTANCESTART
        mul_i_2 : fmul32
        mul_i_2 : fmul32
        port map (
        port map (
                clk => clk,
                clk => clk,
                dpc => dpc,
                a32 => f( 159   downto 128),
                a32 => a( 223   downto 192),
                b32 => f( 191   downto 160),
                b32 => a( 255   downto 224),
                p32 => p( 95    downto 64)
                c32 => s( 127   downto 96)
 
        );
        );
        --!TBXINSTANCESTART
        --!TBXINSTANCESTART
        mul_i_3 : fmul32
        mul_i_3 : fmul32
        port map (
        port map (
                clk => clk,
                clk => clk,
                dpc => dpc,
                a32 => f( 223   downto 192),
                a32 => a( 95    downto 64),
                b32 => f( 255   downto 224),
                b32 => a( 127   downto 96),
                p32 => p( 127   downto 96)
                c32 => s( 63    downto 32)
 
        );
        );
        --!TBXINSTANCESTART
        --!TBXINSTANCESTART
        mul_i_4 : fmul32
        mul_i_4 : fmul32
        port map (
        port map (
                clk => clk,
                clk => clk,
                dpc => dpc,
                a32 => f( 287   downto 256),
                a32 => a( 159   downto 128),
                b32 => f( 319   downto 288),
                b32 => a( 191   downto 160),
                p32 => p( 159   downto 128)
                c32 => s( 95    downto 64)
 
        );
        );
        --!TBXINSTANCESTART
        --!TBXINSTANCESTART
        mul_i_5 : fmul32
        mul_i_5 : fmul32
        port map (
        port map (
                clk => clk,
                clk => clk,
                dpc => dpc,
                a32 => f( 351   downto 320),
                a32 => a( 223   downto 192),
                b32 => f( 383   downto 352),
                b32 => a( 255   downto 224),
                p32 => p( 191   downto 160)
                c32 => s( 127   downto 96)
 
        );
        );
 
 
 
 
 
 
end architecture;
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.