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Line 18... |
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package arithpack is
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package arithpack is
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--! Estados para la maquina de estados.
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--! Estados para la maquina de estados.
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type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
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type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
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--! Estados para el controlador de interrupciones.
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--! Estados para el controlador de interrupciones.
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type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
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type iCtrlState is (WAITING_FOR_A_RFULL_EVENT,INHIBIT_RFULL_INT);
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--! Float data blocks
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--! Float data blocks
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constant floatwidth : integer := 32;
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constant floatwidth : integer := 32;
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constant widthadmemblock : integer := 9;
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constant widthadmemblock : integer := 9;
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Line 68... |
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--! datos de entrada
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--! datos de entrada
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d : in std_logic_vector (31 downto 0);
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d : in std_logic_vector (31 downto 0);
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--! Interrupciones
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--! Interrupciones
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int : out std_logic_vector (7 downto 0);
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int : out std_logic;
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--! Salidas
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--! Salidas
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q : out std_logic_vector (31 downto 0)
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q : out std_logic_vector (31 downto 0)
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num_events : integer ;
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num_events : integer ;
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cycles_to_wait : integer
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cycles_to_wait : integer
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);
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);
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port (
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port (
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clk,rst: in std_logic;
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clk,rst: in std_logic;
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rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
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rfull_event: in std_logic; --! full results queue events
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eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
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eoi_event: in std_logic; --! end of instruction related events
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eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
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int: out std_logic;
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rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
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state: out iCtrlState
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state: out iCtrlState
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);
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);
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end component;
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end component;
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--! Bloque de memorias
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--! Bloque de memorias
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component memblock
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component memblock
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generic (
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blocksize : integer;
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external_readable_widthad : integer;
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external_writeable_widthad : integer
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);
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port (
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port (
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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instrfifo_rd : in std_logic;
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instrfifo_rd : in std_logic;
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resultfifo_wr: in std_logic_vector(8-1 downto 0);
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resultfifo_wr: in std_logic_vector(8-1 downto 0);
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instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
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instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_rd_add : in std_logic_vector(3 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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int_d : in vectorblock08;
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int_d : in vectorblock08;
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status_register : in std_logic_vector(3 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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int_q : out vectorblock12;
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int_q : out vectorblock12;
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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Line 544... |
variable tmp:string (1 to 9);
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variable tmp:string (1 to 9);
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begin
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begin
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write(l,string'("<< "));
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write(l,string'("<< "));
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case i is
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case i is
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when WAITING_FOR_AN_EVENT =>
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when WAITING_FOR_A_RFULL_EVENT =>
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tmp:="WAIT_EVNT";
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tmp:="WAIT_RF_EVNT";
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when FIRING_INTERRUPTIONS =>
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when INHIBIT_RFULL_INT =>
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tmp:="FIRE_INTx";
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tmp:="INHB_RF_INT";
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when SUSPEND =>
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tmp:="SUSPENDED";
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when others =>
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when others =>
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tmp:="ILGL__VAL";
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tmp:="ILGL__VAL";
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end case;
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end case;
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write(l,string'(tmp));
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write(l,string'(tmp));
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write(l,string'(" >>"));
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write(l,string'(" >>"));
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