| Line 22... |
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--! Estados para el controlador de interrupciones.
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--! Estados para el controlador de interrupciones.
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type iCtrlState is (WAITING_FOR_A_RFULL_EVENT,INHIBIT_RFULL_INT);
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type iCtrlState is (WAITING_FOR_A_RFULL_EVENT,INHIBIT_RFULL_INT);
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--! Float data blocks
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--! Float data blocks
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constant floatwidth : integer := 32;
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constant floatwidth : integer := 32;
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--! Control de tamaños de memoria.
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constant widthadmemblock : integer := 9;
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constant widthadmemblock : integer := 9;
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--! Reducció de memoria por mitades
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constant memoryreduction : integer := 1;
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subtype xfloat32 is std_logic_vector(31 downto 0);
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subtype xfloat32 is std_logic_vector(31 downto 0);
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type v3f is array(02 downto 0) of xfloat32;
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type v3f is array(02 downto 0) of xfloat32;
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--! Constantes para definir
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--! Constantes para definir
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| Line 38... |
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type vectorblock08 is array (07 downto 0) of xfloat32;
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type vectorblock08 is array (07 downto 0) of xfloat32;
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type vectorblock06 is array (05 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock06 is array (05 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock04 is array (03 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock04 is array (03 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock03 is array (02 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock03 is array (02 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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type vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1-memoryreduction downto 0);
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--! Constante de reseteo
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--! Constante de reseteo
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constant rstMasterValue : std_logic :='0';
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constant rstMasterValue : std_logic :='0';
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--! Constantes periodicas.
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--! Constantes periodicas.
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Line 198... |
width_byteena_a : natural
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width_byteena_a : natural
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);
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);
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port (
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port (
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wren_a : in std_logic;
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wren_a : in std_logic;
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clock0 : in std_logic;
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clock0 : in std_logic;
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address_a : in std_logic_vector(8 downto 0);
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address_a : in std_logic_vector(widthadmemblock-1-memoryreduction downto 0);
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address_b : in std_logic_vector(8 downto 0);
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address_b : in std_logic_vector(widthadmemblock-1-memoryreduction downto 0);
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rden_b : in std_logic;
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rden_b : in std_logic;
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q_b : out std_logic_vector(31 downto 0);
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q_b : out std_logic_vector(31 downto 0);
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data_a : in std_logic_vector(31 downto 0)
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data_a : in std_logic_vector(31 downto 0)
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);
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);
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