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--! @file opcoder.vhd
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--! @file dpc.vhd
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--! @brief Decodificador de operacion.
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--! @brief Decodificador de operacion.
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--! @author Julián Andrés Guarín Reyes.
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--! @author Julián Andrés Guarín Reyes.
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- opcoder.vhd
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-- dpc.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
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library ieee;
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library ieee;
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--! Paquete de definicion estandard de logica. Standard logic definition pack.
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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entity dpc is
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use work.arithpack.all;
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--! La entidad opcoder es la etapa combinatoria que decodifica la operacion que se va a realizar.
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--! \n\n
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--! Las entradas a esta descripción son: los vectores A,B,C,D, las entradas opcode y addcode. Las salidas del decodificador, estarán conectadas a las entradas de los 6 multiplicadores de una entidad uf. Los operandos de los multiplicadores, también conocidos como factores, son las salida m0f0, m0f1 para el multiplicador 1 y así hasta el multiplicador 5. Básicamente lo que opera aquí en esta descripción es un multiplexor, el cual selecciona a través de opcode y addcode qué componentes de los vectores se conectaran a los operandos de los multiplicadores.
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entity opcoder is
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generic (
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generic (
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width : integer := 18;
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width : integer := 32
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structuralDescription : string:= "NO"
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);
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);
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port (
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port (
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Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (width-1 downto 0);
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (width-1 downto 0);
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prd32blko,add32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores y los 6 sumadores.
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sqr32blko,inv32blko : in std_logic_vector ((02*width)-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32o : in std_logic_vector ( width-1 downto 0); --! Salida de la cola intermedia.
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instr3 : in std_logic_vector ( 2 downto 0); --! Opcode con la instrucción.
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fifo32i : out std_logic_vector ( width-1 downto 0); --! Entrada a la cola intermedia.
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prd32blki,add32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 sumandos y de los 12 factores en los 2 bloques de suma y el bloque de multiplicación respectivamente.
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add32blks : out std_logic_vector ( 1 downto 0); --! Signos de operación que entran en los 2 bloques de suma.
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resultoutput : out std_logic_vector ((06*width)-1 downto 0) --! 6 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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opcode,addcode : in std_logic
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);
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);
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end entity;
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end dpc;
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--! Arquitectura del decodificador de operación.
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architecture dpc_arch of dpc is
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--! El bloque de arquitectura del decodificador es simplemente una cascada de multiplexores. La selección se hace en función de las señales appcode y addcode\n
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component scfifo
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--! La siguiente tabla describe el comportamiento de los multiplexores:\n
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generic (
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--! \n\n
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add_ram_output_register : string;
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--!
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intended_device_family : string;
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--! <table>
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lpm_hint : string;
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--! <tr><th></th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th></tr> <tr><td>m0</td><td>0</td><td>0</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>0</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>0</td><td>1</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>1</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>0</td><td>Ay</td><td>Bz</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>Bz</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>1</td><td>Cy</td><td>Dz</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dz</td><td>m3</td></tr> <tr><td>m1</td><td>0</td><td>0</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>0</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>0</td><td>1</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>1</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>0</td><td>Az</td><td>By</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>By</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>1</td><td>Cz</td><td>Dy</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dy</td><td>m4</td></tr> <tr><td>m2</td><td>0</td><td>0</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>0</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>0</td><td>1</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>1</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>0</td><td>Az</td><td>Bx</td><td> </td><td>1</td><td>0</td><td>Ay</td><td>Bx</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>1</td><td>Cz</td><td>Dx</td><td> </td><td>1</td><td>1</td><td>Cy</td><td>Dx</td><td>m5</td></tr></table>
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lpm_numwords : natural;
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--! \n\n
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lpm_showahead : string;
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--! Por ejemplo para ver la tabla de verdad del m0f0, consultar el registro (línea) m0 y el atributo (columna) f0.\n
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lpm_type : string;
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lpm_width : natural;
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lpm_widthu : natural;
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overflow_checking : string;
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underflow_checking : string;
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use_eab : string
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);
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port (
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rd
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)
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architecture opcoder_arch of opcoder is
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constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
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constant cz : integer := 06;constant cy : integer := 07;constant cx : integer := 08;constant dz : integer := 09;constant dy : integer := 10;constant dx : integer := 11;
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constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
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constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
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constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
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constant s6 : integer := 06;constant s7 : integer := 07;constant s8 : integer := 08;constant s9 : integer := 09;constant s10: integer := 10;constant s11: integer := 11;
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constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;constant aa : integer := 03;constant ab : integer := 04;constant ac : integer := 05;
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constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
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constant sqrt320 : integer := 00;
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constant sqrt321 : integer := 01;
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constant invr320 : integer := 00;
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constant invr321 : integer := 01;
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock06 is array (05 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(width-1 downto 0);
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signal sparaminput,sfactor,ssumando : vectorblock12;
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signal sprd32blk,sadd32blk,sresult : vectorblock06;
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signal ssqr32blk,sinv32blk : vectorblock02;
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signal aycy,bzdz,azcz,bydy,bxdx,axcx: std_logic_vector(width-1 downto 0);
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begin
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begin
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--! Proceso que describe las 2 etapas de multiplexores.
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--! Proceso que describe las 2 etapas de multiplexores. Una corresponde al selector addcode, que selecciona con que operadores realizará la operación producto cruz, es decir, seleccionará si realiza la operación AxB ó CxD. En el caso del producto punto, esta etapa de multiplexación no tendrá repercusión en el resultado de la deocdificación de la operación. La otra etapa utiliza el selector opcode, el cual decide si usa los operandos decodificados en la primera etapa de multiplexores, en el caso de que opcode sea 1, seleccionando la operación producto cruz, o por el contrario seleccionando una decodificación de operadores que lleven a cabo la operación producto punto.
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originalMuxGen:
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--! Connect stuff ....
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if structuralDescription="NO" generate
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stuff12:
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for i in 11 downto 0 generate
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sparaminput(i) <= paraminput(i*width+width-1 downto i*width);
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prd32blki(i*width+width-1 downto i*width) <= sfactor(i);
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add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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end generate stuff12;
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stuff06:
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for i in 05 downto 0 generate
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sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
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sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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end generate stuff06;
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stuff02:
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for i in 05 downto 0 generate
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ssqr32blk(i) <= sqr32blko(i*width+width-1 downto i*width);
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sinv32blk(i) <= inv32blko(i*width+width-1 downto i*width);
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end generate stuff02;
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procOpcoder:
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process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,aycy,bzdz,azcz,bydy,bxdx,axcx,opcode,addcode)
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begin
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case (addcode) is
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-- Estamos ejecutando CxD
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when '1'=>
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aycy <= Cy;
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bzdz <= Dz;
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azcz <= Cz;
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bydy <= Dy;
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axcx <= Cx;
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bxdx <= Dx;
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when others =>
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-- Estamos ejecutando AxB
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aycy <= Ay;
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bzdz <= Bz;
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azcz <= Az;
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bydy <= By;
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axcx <= Ax;
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bxdx <= Bx;
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end case;
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case (opcode) is
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-- Estamos ejecutando Producto Cruz
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when '1' =>
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m0f0 <= aycy;
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m0f1 <= bzdz;
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m1f0 <= azcz;
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m1f1 <= bydy;
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m2f0 <= axcx;
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m2f1 <= bzdz;
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m3f0 <= azcz;
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m3f1 <= bxdx;
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m4f0 <= axcx;
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m4f1 <= bydy;
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m5f0 <= aycy;
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m5f1 <= bxdx;
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when others =>
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-- Estamos ejecutando Producto Punto
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m0f0 <= Ax;
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m0f1 <= Bx;
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m1f0 <= Ay;
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m1f1 <= By;
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m2f0 <= Az;
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m2f1 <= Bz;
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m3f0 <= Cx;
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m3f1 <= Dx;
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m4f0 <= Cy;
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m4f1 <= Dy;
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m5f0 <= Cz;
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m5f1 <= Dz;
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end case;
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end process procOpcoder;
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end generate originalMuxGen;
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fastMuxGen:
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if structuralDescription="YES" generate
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mux0 : fastmux generic map (width) port map (ay,cy,addcode,aycy);
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mux1 : fastmux generic map (width) port map (bz,dz,addcode,bzdz);
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mux2 : fastmux generic map (width) port map (az,cz,addcode,azcz);
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mux3 : fastmux generic map (width) port map (by,dy,addcode,bydy);
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mux4 : fastmux generic map (width) port map (bx,dx,addcode,bxdx);
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mux5 : fastmux generic map (width) port map (ax,cx,addcode,axcx);
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-- Segunda etapa de multiplexores
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muxa : fastmux generic map (width) port map (ax,aycy,opcode,m0f0);
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muxb : fastmux generic map (width) port map (bx,bzdz,opcode,m0f1);
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muxc : fastmux generic map (width) port map (ay,azcz,opcode,m1f0);
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muxd : fastmux generic map (width) port map (by,bydy,opcode,m1f1);
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muxe : fastmux generic map (width) port map (az,azcz,opcode,m2f0);
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muxf : fastmux generic map (width) port map (bz,bxdx,opcode,m2f1);
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muxg : fastmux generic map (width) port map (cx,axcx,opcode,m3f0);
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muxh : fastmux generic map (width) port map (dx,bzdz,opcode,m3f1);
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muxi : fastmux generic map (width) port map (cy,axcx,opcode,m4f0);
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muxj : fastmux generic map (width) port map (dy,bydy,opcode,m4f1);
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muxk : fastmux generic map (width) port map (cz,aycy,opcode,m5f0);
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muxl : fastmux generic map (width) port map (dz,bxdx,opcode,m5f1);
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end generate fastMuxGen;
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fifoconnection_proces:process(instr3)
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begin
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case (instr3) is
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end process;
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end opcoder_arch;
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end dpc_arch;
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