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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity dpc is
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entity dpc is
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generic (
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generic (
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width : integer := 32;
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width : integer := 32
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external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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);
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);
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port (
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port (
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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--! Signo de los 3 primeros sumadores
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--! Signo de los 3 primeros sumadores
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mul:process(unary,addsub,crossprod,scalar,sparaminput,sinv32blk,sprd32blk,sdpfifo_q,snormfifo_q)
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mul:process(unary,addsub,crossprod,scalar,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
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begin
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begin
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if unary='1' then
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if unary='1' then
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--! Magnitud y normalizacion
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--! Magnitud y normalizacion
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ssumando(s4) <= sparaminput(az);
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ssumando(s4) <= sparaminput(az);
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ssumando(s5) <= sparaminput(bz);
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ssumando(s5) <= sparaminput(bz);
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else
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else
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ssumando(s0) <= sprd32blk(p0);
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ssumando(s0) <= sprd32blk(p0);
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ssumando(s1) <= sprd32blk(p1);
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ssumando(s1) <= sprd32blk(p1);
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ssumando(s2) <= sdpfifo_q(dpfifoab);
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if crossprod='0' then
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ssumando(s3) <= sprd32blk(p2);
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ssumando(s2) <= sadd32blk(a0);
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ssumando(s3) <= sdpfifo_q(dpfifoab);
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else
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ssumando(s2) <= sprd32blk(p2);
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ssumando(s3) <= sprd32blk(p3);
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end if;
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ssumando(s4) <= sprd32blk(p4);
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ssumando(s4) <= sprd32blk(p4);
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ssumando(s5) <= sprd32blk(p5);
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ssumando(s5) <= sprd32blk(p5);
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end if;
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end if;
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end process;
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end process;
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