| Line 27... |
Line 27... |
generic (
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generic (
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width : integer := 32
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width : integer := 32
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--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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);
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);
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port (
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port (
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clk : in std_logic;
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x26_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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fifo32x26_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
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fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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scalar : in std_logic;
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scalar : in std_logic;
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sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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| Line 91... |
Line 93... |
stuff08:
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stuff08:
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for i in 07 downto 0 generate
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for i in 07 downto 0 generate
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add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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end generate stuff08;
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end generate stuff08;
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stuff06:
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for i in 05 downto 0 generate
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process (clk)
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sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
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begin
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end generate stuff06;
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if clk'event and clk='1' then
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for i 05 downto 0 loop
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sprd32blk(p0) <= prd32blko(i*width+width-1 downto i*width);
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end loop;
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end if;
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end process;
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stuff04:
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stuff04:
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for i in 03 downto 0 generate
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for i in 03 downto 1 generate
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sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
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sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
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end generate stuff04;
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end generate stuff04;
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process (clk)
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begin
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if clk'event and clk='1' then
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sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
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sinv32blk <= inv32blko;
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end if;
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end process;
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stuff03:
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stuff03:
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for i in 02 downto 0 generate
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for i in 02 downto 0 generate
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snormfifo_q(i) <= fifo32x26_q(i*width+width-1 downto i*width);
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snormfifo_q(i) <= fifo32x26_q(i*width+width-1 downto i*width);
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fifo32x26_d(i*width+width-1 downto i*width) <= snormfifo_d(i);
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fifo32x26_d(i*width+width-1 downto i*width) <= snormfifo_d(i);
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end generate stuff03;
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end generate stuff03;
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| Line 113... |
Line 128... |
end generate stuff02;
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end generate stuff02;
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fifo32x09_d <= sprd32blk(p3)&sprd32blk(p2);
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fifo32x09_d <= sprd32blk(p3)&sprd32blk(p2);
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sinv32blk <= inv32blko;
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ssqr32blk <= sqr32blko;
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ssqr32blk <= sqr32blko;
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--! Salidas de los distintos resultados;
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--! Colas de salida de los distintos resultados;
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sresult(0) <= ssqr32blk;
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sresult(0) <= ssqr32blk;
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sresult(1) <= sadd32blk(a0);
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sresult(1) <= sadd32blk(a0);
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sresult(2) <= sadd32blk(a1);
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sresult(2) <= sadd32blk(a1);
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sresult(3) <= sadd32blk(a2);
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sresult(3) <= sadd32blk(a2);
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sresult(4) <= sadd32blk(aa);
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sresult(4) <= sadd32blk(aa);
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| Line 131... |
Line 145... |
--! Cola de normalizacion
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--! Cola de normalizacion
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snormfifo_d(qx) <= sparaminput(ax);
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snormfifo_d(qx) <= sparaminput(ax);
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snormfifo_d(qy) <= sparaminput(ay);
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snormfifo_d(qy) <= sparaminput(ay);
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snormfifo_d(qz) <= sparaminput(az);
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snormfifo_d(qz) <= sparaminput(az);
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--! Signo de los 3 primeros sumadores
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--! La entrada al inversor SIEMPRE viene con la salida de la raiz cuadrada
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inv32blki <= sqr32blko;
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--! La entrada de la ra’z cuadrada SIEMPRE viene con la salida del sumador 1.
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sqr32blki <= sadd32blk(a1);
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--! Conectar las entradas del sumador a, a la salida
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ssumando(s6) <= sadd32blk(a2);
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ssumando(s7) <= sdpfifo_q(dpfifocd);
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mul:process(unary,addsub,crossprod,scalar,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
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mul:process(unary,addsub,crossprod,scalar,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
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begin
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begin
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| Line 197... |
Line 220... |
sfactor(f10) <= sparaminput(cz) ;
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sfactor(f10) <= sparaminput(cz) ;
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sfactor(f11) <= sparaminput(dx) ;
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sfactor(f11) <= sparaminput(dx) ;
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end if;
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end if;
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ssumando(s6) <= sadd32blk(a2);
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ssumando(s7) <= sdpfifo_q(dpfifocd);
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if addsub='1' then
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if addsub='1' then
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ssumando(s0) <= sparaminput(ax);
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ssumando(s0) <= sparaminput(ax);
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ssumando(s1) <= sparaminput(bx);
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ssumando(s1) <= sparaminput(bx);
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ssumando(s2) <= sparaminput(ay);
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ssumando(s2) <= sparaminput(ay);
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ssumando(s3) <= sparaminput(by);
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ssumando(s3) <= sparaminput(by);
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