| Line 27... |
Line 27... |
generic (
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generic (
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width : integer := 32
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width : integer := 32
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--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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);
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);
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port (
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port (
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clk : in std_logic;
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clk,ena : in std_logic;
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x26_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
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fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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scalar : in std_logic;
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scalar : in std_logic;
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sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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| Line 94... |
Line 94... |
for i in 07 downto 0 generate
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for i in 07 downto 0 generate
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add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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end generate stuff08;
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end generate stuff08;
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process (clk)
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register_products_outputs:
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process (clk,ena)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' and ena='1' then
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for i 05 downto 0 loop
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for i 05 downto 0 loop
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sprd32blk(p0) <= prd32blko(i*width+width-1 downto i*width);
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sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
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end loop;
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end loop;
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end if;
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end if;
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end process;
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end process;
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stuff04:
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register_adder0_and_inversor_output:
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for i in 03 downto 1 generate
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process (clk,ena)
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sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
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end generate stuff04;
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process (clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' and ena='1' then
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sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
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sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
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sinv32blk <= inv32blko;
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sinv32blk <= inv32blko;
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end if;
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end if;
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end process;
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end process;
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stuff04:
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for i in 03 downto 1 generate
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sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
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end generate stuff04;
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stuff03:
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stuff03:
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for i in 02 downto 0 generate
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for i in 02 downto 0 generate
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snormfifo_q(i) <= fifo32x26_q(i*width+width-1 downto i*width);
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snormfifo_q(i) <= fifo32x23_q(i*width+width-1 downto i*width);
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fifo32x26_d(i*width+width-1 downto i*width) <= snormfifo_d(i);
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fifo32x26_d(i*width+width-1 downto i*width) <= snormfifo_d(i);
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end generate stuff03;
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end generate stuff03;
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stuff02:
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stuff02:
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for i in 01 downto 0 generate
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for i in 01 downto 0 generate
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