| Line 27... |
Line 27... |
generic (
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generic (
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width : integer := 32
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width : integer := 32
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--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
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);
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);
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port (
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port (
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clk,ena : in std_logic;
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clk,ena,rst : in std_logic;
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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| Line 41... |
Line 41... |
sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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res567w,res13w,res2w,res0w,res4w,fifo32x09_w,fifo32x23_w,fifo32x09_r,fifo32x23_r: out std_logic;
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resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 6 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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);
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end dpc;
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end dpc;
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|
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architecture dpc_arch of dpc is
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architecture dpc_arch of dpc is
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|
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| Line 78... |
Line 78... |
signal sadd32blk : vectorblock04;
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signal sadd32blk : vectorblock04;
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signal snormfifo_q,snormfifo_d : vectorblock03;
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signal snormfifo_q,snormfifo_d : vectorblock03;
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signal sdpfifo_q : vectorblock02;
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signal sdpfifo_q : vectorblock02;
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signal ssqr32blk,sinv32blk : std_logic_vector(width-1 downto 0);
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signal ssqr32blk,sinv32blk : std_logic_vector(width-1 downto 0);
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signal sync_chain : std_logic_vector(27 downto 0);
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signal sync_chain_d : std_logic;
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constant rstMasterValue : std_logic := '0';
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|
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begin
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begin
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--! Cadena de sincronización: 28 posiciones.
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sync_chain_proc:
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process(clk,rst)
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begin
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if rst=rstMasterValue then
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sync_chain <= (others => '0');
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elsif clk'event and clk='1' then
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sync_chain(0) <= sync_chain_d;
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for i in 27 downto 1 loop
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sync_chain(i) <= sync_chain(i-1);
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end loop;
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end if;
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end process sync_chain_proc;
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--! Escritura en las colas de resultados y escritura/lectura en las colas intermedias mediante cadena de resultados.
|
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fifo32x09_w <= sync_chain(4);
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fifo32x23_w <= sync_chain(0);
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fifo32x09_r <= sync_chain();
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fifo32x23_r <= sync_chain();
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|
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res0w <= sync_chain(22);
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res4w <= sync_chain(20);
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sync_chain_comb:
|
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process (sync_chain,addsub,crossprod)
|
|
begin
|
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if unary='1' then
|
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res567w <= sync_chain(27);
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else
|
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res567w <= sync_chain(3);
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end if;
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|
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if addsub='1' then
|
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res13w <= sync_chain(8);
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res2w <= sync_chain(8);
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else
|
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res13w <= sync_chain(12);
|
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if crossprod='1' then
|
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res2w <= res13w;
|
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else
|
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res2w <= sync_chain(21);
|
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end if;
|
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end if;
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end process sync_chain_comb;
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|
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--! El siguiente código sirve para conectar arreglos a señales std_logic_1164, simplemente son abstracciones a nivel de código y no representará cambios en la síntesis.
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stuff12:
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stuff12:
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for i in 11 downto 0 generate
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for i in 11 downto 0 generate
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sparaminput(i) <= paraminput(i*width+width-1 downto i*width);
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sparaminput(i) <= paraminput(i*width+width-1 downto i*width);
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prd32blki(i*width+width-1 downto i*width) <= sfactor(i);
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prd32blki(i*width+width-1 downto i*width) <= sfactor(i);
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end generate stuff12;
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end generate stuff12;
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|
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stuff08:
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stuff08:
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for i in 07 downto 0 generate
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for i in 07 downto 0 generate
|
add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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end generate stuff08;
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end generate stuff08;
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|
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register_products_outputs:
|
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process (clk,ena)
|
|
begin
|
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if clk'event and clk='1' and ena='1' then
|
|
for i in 05 downto 0 loop
|
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sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
|
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end loop;
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end if;
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end process;
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|
|
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register_adder0_and_inversor_output:
|
|
process (clk,ena)
|
|
begin
|
|
if clk'event and clk='1' and ena='1' then
|
|
sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
|
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sinv32blk <= inv32blko;
|
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end if;
|
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end process;
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|
|
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stuff04:
|
stuff04:
|
for i in 03 downto 1 generate
|
for i in 03 downto 1 generate
|
sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
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sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
|
end generate stuff04;
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end generate stuff04;
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|
|
| Line 129... |
Line 155... |
|
|
stuff02:
|
stuff02:
|
for i in 01 downto 0 generate
|
for i in 01 downto 0 generate
|
sdpfifo_q(i) <= fifo32x09_q(i*width+width-1 downto i*width);
|
sdpfifo_q(i) <= fifo32x09_q(i*width+width-1 downto i*width);
|
end generate stuff02;
|
end generate stuff02;
|
|
|
|
--! El siguiente código sirve para conectar arreglos a señales std_logic_1164, son abstracciones de código también, sin embargo se realizan a través de registros.
|
|
register_products_outputs:
|
|
process (clk)
|
|
begin
|
|
if clk'event and clk='1' then
|
|
for i in 05 downto 0 loop
|
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sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
|
|
end loop;
|
|
end if;
|
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end process;
|
|
--! Los productos del multiplicador 2 y 3, ya registrados dentro de dpc van a la cola intermedia del producto punto (fifo32x09_d)
|
fifo32x09_d <= sprd32blk(p3)&sprd32blk(p2);
|
fifo32x09_d <= sprd32blk(p3)&sprd32blk(p2);
|
|
register_adder0_and_inversor_output:
|
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process (clk)
|
|
begin
|
|
if clk'event and clk='1' then
|
|
sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
|
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sinv32blk <= inv32blko;
|
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end if;
|
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end process;
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|
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|
|
|
|
|
|
|
|
ssqr32blk <= sqr32blko;
|
ssqr32blk <= sqr32blko;
|
|
|
