| Line 41... |
Line 41... |
sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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res567w,res13w,res2w,res0w,res4w,fifo32x09_w,fifo32x23_w,fifo32x09_r,fifo32x23_r: out std_logic;
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res567w,res13w,res2w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
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res0w,res4w,fifo32x09_w : out std_logic;
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fifo32x23_w,fifo32x09_r : out std_logic;
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fifo32x23_r : out std_logic;
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res567f,res13f : in std_logic; --! Entradas de la señal de full de las colas de resultados.
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res2f,res0f : in std_logic;
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resf : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operación está en curso.
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resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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);
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end dpc;
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end dpc;
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architecture dpc_arch of dpc is
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architecture dpc_arch of dpc is
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| Line 70... |
Line 76... |
type vectorblock04 is array (03 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock04 is array (03 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock03 is array (02 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock03 is array (02 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(width-1 downto 0);
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signal sparaminput,sfactor : vectorblock12;
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signal sparaminput,sfactor : vectorblock12;
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signal ssumando,sresult : vectorblock08;
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signal ssumando,sresult : vectorblock08;
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signal sprd32blk : vectorblock06;
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signal sprd32blk : vectorblock06;
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signal sadd32blk : vectorblock04;
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signal sadd32blk : vectorblock04;
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signal snormfifo_q,snormfifo_d : vectorblock03;
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signal snormfifo_q,snormfifo_d : vectorblock03;
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signal sdpfifo_q : vectorblock02;
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signal sdpfifo_q : vectorblock02;
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signal ssqr32blk,sinv32blk : std_logic_vector(width-1 downto 0);
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signal ssqr32blk,sinv32blk : std_logic_vector(width-1 downto 0);
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signal ssync_chain : std_logic_vector(28 downto 0);
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signal ssync_chain : std_logic_vector(28 downto 0);
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signal ssync_chain_d : std_logic;
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signal ssync_chain_d : std_logic;
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constant rstMasterValue : std_logic := '0';
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constant rstMasterValue : std_logic := '0';
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|
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begin
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begin
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--! Cadena de sincronización: 29 posiciones.
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--! Cadena de sincronización: 29 posiciones.
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| Line 99... |
Line 107... |
ssync_chain(i) <= ssync_chain(i-1);
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ssync_chain(i) <= ssync_chain(i-1);
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end loop;
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end loop;
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end if;
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end if;
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end process sync_chain_proc;
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end process sync_chain_proc;
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--! Escritura en las colas de resultados y escritura/lectura en las colas intermedias mediante cadena de resultados.
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--! Escritura en las colas de resultados y escritura/lectura en las colas intermedias mediante cadena de resultados.
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fifo32x09_w <= ssync_chain(4);
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fifo32x09_w <= ssync_chain(5);
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fifo32x23_w <= ssync_chain(0);
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fifo32x23_w <= ssync_chain(1);
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fifo32x09_r <= ssync_chain(12);
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fifo32x09_r <= ssync_chain(13);
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fifo32x23_r <= ssync_chain(23);
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fifo32x23_r <= ssync_chain(24);
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res0w <= ssync_chain(23);
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res0w <= ssync_chain(22);
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res4w <= ssync_chain(21);
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res4w <= ssync_chain(20);
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sync_chain_comb:
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sync_chain_comb:
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process (ssync_chain,addsub,crossprod,unary)
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process (ssync_chain,addsub,crossprod,unary)
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begin
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begin
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if unary='1' then
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if unary='1' then
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res567w <= ssync_chain(27);
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res567w <= ssync_chain(28);
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else
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else
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res567w <= ssync_chain(3);
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res567w <= ssync_chain(4);
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end if;
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end if;
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|
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if addsub='1' then
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if addsub='1' then
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res13w <= ssync_chain(8);
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res13w <= ssync_chain(9);
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res2w <= ssync_chain(8);
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res2w <= ssync_chain(9);
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else
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else
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res13w <= ssync_chain(12);
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res13w <= ssync_chain(13);
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if crossprod='1' then
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if crossprod='1' then
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res2w <= ssync_chain(12);
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res2w <= ssync_chain(13);
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else
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else
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res2w <= ssync_chain(21);
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res2w <= ssync_chain(22);
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end if;
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end if;
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end if;
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end if;
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end process sync_chain_comb;
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end process sync_chain_comb;
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| Line 213... |
Line 220... |
--! Conectar las entradas del sumador a, a la salida
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--! Conectar las entradas del sumador a, a la salida
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ssumando(s6) <= sadd32blk(a2);
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ssumando(s6) <= sadd32blk(a2);
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ssumando(s7) <= sdpfifo_q(dpfifocd);
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ssumando(s7) <= sdpfifo_q(dpfifocd);
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fullQ:process(res0f,res13f,res2f,res567f,unary,crossprod,addsub)
|
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begin
|
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if unary='0' then
|
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if crossprod='1' or addsub='1' then
|
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resf <= res13f;
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else
|
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resf <= res2f;
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end if;
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elsif crossprod='1' or addsub='1' then
|
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resf <= res567f;
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else
|
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resf <= res0f;
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end if;
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end process;
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mul:process(unary,addsub,crossprod,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
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mul:process(unary,addsub,crossprod,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
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begin
|
begin
|
|
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sfactor(f4) <= sparaminput(az);
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sfactor(f4) <= sparaminput(az);
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if unary='1' then
|
if unary='1' then
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