| Line 114... |
Line 114... |
fifo32x09_w <= ssync_chain(5);
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fifo32x09_w <= ssync_chain(5);
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fifo32x23_w <= ssync_chain(1);
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fifo32x23_w <= ssync_chain(1);
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fifo32x09_r <= ssync_chain(13);
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fifo32x09_r <= ssync_chain(13);
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fifo32x23_r <= ssync_chain(24);
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fifo32x23_r <= ssync_chain(24);
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res0w <= ssync_chain(23);
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res0w <= ssync_chain(23);
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res4w <= ssync_chain(21);
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res4w <= ssync_chain(22);
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sync_chain_comb:
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sync_chain_comb:
|
process (ssync_chain,addsub,crossprod,unary)
|
process (ssync_chain,addsub,crossprod,unary)
|
begin
|
begin
|
if unary='1' then
|
if unary='1' then
|
res567w <= ssync_chain(28);
|
res567w <= ssync_chain(28);
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| Line 150... |
Line 150... |
for i in 07 downto 0 generate
|
for i in 07 downto 0 generate
|
add32blki(i*width+width-1 downto i*width) <= ssumando(i);
|
add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
|
resultoutput(i*width+width-1 downto i*width) <= sresult(i);
|
end generate stuff08;
|
end generate stuff08;
|
stuff04:
|
stuff04:
|
for i in 03 downto 1 generate
|
for i in 02 downto 1 generate
|
sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
|
sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
|
end generate stuff04;
|
end generate stuff04;
|
|
|
|
|
stuff03:
|
stuff03:
|
| Line 177... |
Line 177... |
sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
|
sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end process;
|
end process;
|
--! Los productos del multiplicador 2 y 3, ya registrados dentro de dpc van a la cola intermedia del producto punto (fifo32x09_d)
|
--! Los productos del multiplicador 2 y 3, ya registrados dentro de dpc van a la cola intermedia del producto punto (fifo32x09_d)
|
|
--! Los unicos resultados de sumandos que de nuevo entran al DataPathControl (observar la pestaña del documento de excel)
|
|
|
fifo32x09_d <= sprd32blk(p3)&sprd32blk(p2);
|
fifo32x09_d <= sprd32blk(p3)&sprd32blk(p2);
|
register_adder0_and_inversor_output:
|
register_adder0_and_inversor_output:
|
process (clk)
|
process (clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
|
sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
|
|
sadd32blk(aa) <= add32blko(aa*width+width-1 downto aa*width);
|
sinv32blk <= inv32blko;
|
sinv32blk <= inv32blko;
|
end if;
|
end if;
|
end process;
|
end process;
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