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--! @file dpc.vhd
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--! @brief Decodificador de operacion.
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- dpc.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all;
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use work.arithpack.all;
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entity dpc is
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port (
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clk,rst : in std_logic;
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paraminput : in vectorblock12; --! Vectores A,B,C,D
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prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.
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add32blko : in vectorblock04; --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (floatwidth-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x23_q : in std_logic_vector (03*floatwidth-1 downto 0); --! Salida de la cola intermedia.
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fifo32x09_q : in std_logic_vector (02*floatwidth-1 downto 0); --! Salida de las colas de producto punto.
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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eoi_int : in std_logic; --! Señal de interrupción de final de instrucción.
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eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrupción de final de instrucción pero esta vez va asociada a la instruccón UCA.
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sqr32blki,inv32blki : out std_logic_vector (floatwidth-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*floatwidth-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x09_d : out std_logic_vector (02*floatwidth-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out vectorblock08; --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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fifo32x09_w : out std_logic;
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fifo32x23_w,fifo32x09_r : out std_logic;
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fifo32x23_r : out std_logic;
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resf_vector : in std_logic_vector (3 downto 0); --! Entradas de la señal de full de las colas de resultados.
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resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operación que está en curso.
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resultoutput : out vectorblock08 --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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end entity;
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architecture dpc_arch of dpc is
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constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;
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constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
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constant cz : integer := 06;constant cy : integer := 07;constant cx : integer := 08;constant dz : integer := 09;constant dy : integer := 10;constant dx : integer := 11;
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constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
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constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
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constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
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constant s6 : integer := 06;constant s7 : integer := 07;
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constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;constant aa : integer := 03;
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constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
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constant dpfifoab : integer := 00;
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constant dpfifocd : integer := 01;
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signal sparaminput : vectorblock12;
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--!TBXSTART:FACTORS_N_ADDENDS
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signal sfactor : vectorblock12;
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signal ssumando : vectorblock08;
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signal sdpfifo_q : vectorblock02;
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--!TBXEND
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--!TBXSTART:ARITHMETIC_RESULTS
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signal sresult : vectorblock08;
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signal sprd32blk : vectorblock06;
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signal sadd32blk : vectorblock04;
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signal ssqr32blk,sinv32blk : xfloat32;
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signal snormfifo_q,snormfifo_d : vectorblock03;
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--!TBXEND
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--!TBXSTART:SYNC_CHAIN
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signal ssync_chain : std_logic_vector(25 downto 1);
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signal sres567w,sres123w,sres2w : std_logic;
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signal sres0w,sres4w : std_logic;
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--!TBXEND
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--! Entradas
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