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--! @file dpc.vhd
 
--! @brief Decodificador de operacion. 
 
--! @author Julián Andrés Guarín Reyes
 
--------------------------------------------------------------
 
-- RAYTRAC
 
-- Author Julian Andres Guarin
 
-- dpc.vhd
 
-- This file is part of raytrac.
 
-- 
 
--     raytrac is free software: you can redistribute it and/or modify
 
--     it under the terms of the GNU General Public License as published by
 
--     the Free Software Foundation, either version 3 of the License, or
 
--     (at your option) any later version.
 
-- 
 
--     raytrac is distributed in the hope that it will be useful,
 
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--     GNU General Public License for more details.
 
-- 
 
--     You should have received a copy of the GNU General Public License
 
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
 
 
 
library ieee;
 
use ieee.std_logic_1164.all;
 
 
 
use work.arithpack.all;
 
 
 
 
 
entity dpc is
 
 
 
        port (
 
                clk,rst                                 : in    std_logic;
 
                paraminput                              : in    vectorblock12;                                                                  --! Vectores A,B,C,D
 
                prd32blko                               : in    vectorblock06;  --! Salidas de los 6 multiplicadores.
 
                add32blko                               : in    vectorblock04;  --! Salidas de los 4 sumadores.
 
                sqr32blko,inv32blko             : in    std_logic_vector (floatwidth-1 downto 0);                --! Salidas de la raiz cuadradas y el inversor.
 
                fifo32x23_q                             : in    std_logic_vector (03*floatwidth-1 downto 0);             --! Salida de la cola intermedia.
 
                fifo32x09_q                             : in    std_logic_vector (02*floatwidth-1 downto 0);     --! Salida de las colas de producto punto. 
 
                unary,crossprod,addsub  : in    std_logic;                                                                      --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D). 
 
                sync_chain_0                    : in    std_logic;                                                                      --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
 
                eoi_int                                 : in    std_logic;                                                                      --! Se&ntilde;al de interrupci&oacute;n de final de instrucci&oacute;n.
 
                eoi_demuxed_int                 : out   std_logic_vector (3 downto 0);                           --! Se&ntilde;al de interrupci&oacute;n de final de instrucci&oacute;n pero esta vez va asociada a la instrucc&oacute;n UCA.
 
                sqr32blki,inv32blki             : out   std_logic_vector (floatwidth-1 downto 0);                --! Salidas de las 2 raices cuadradas y los 2 inversores.
 
                fifo32x26_d                             : out   std_logic_vector (03*floatwidth-1 downto 0);             --! Entrada a la cola intermedia para la normalizaci&oacute;n.
 
                fifo32x09_d                             : out   std_logic_vector (02*floatwidth-1 downto 0);             --! Entrada a las colas intermedias del producto punto.         
 
                prd32blki                               : out   vectorblock12;  --! Entrada de los 12 factores en el bloque de multiplicaci&oacute;n respectivamente.
 
                add32blki                               : out   vectorblock08;  --! Entrada de los 8 sumandos del bloque de 4 sumadores.  
 
                resw                                    : out   std_logic_vector (4 downto 0);                           --! Salidas de escritura y lectura en las colas de resultados.
 
                fifo32x09_w                             : out   std_logic;
 
                fifo32x23_w,fifo32x09_r : out   std_logic;
 
                fifo32x23_r                             : out   std_logic;
 
                resf_vector                             : in    std_logic_vector (3 downto 0);                           --! Entradas de la se&ntilde;al de full de las colas de resultados. 
 
                resf_event                              : out   std_logic;                                                                      --! Salida decodificada que indica que la cola de resultados de la operaci&oacute;n que est&aacute; en curso.
 
                resultoutput                    : out   vectorblock08 --! 8 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores. 
 
        );
 
end entity;
 
 
 
architecture dpc_arch of dpc is
 
 
 
        constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;
 
        constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
 
        constant cz : integer := 06;constant cy : integer := 07;constant cx : integer := 08;constant dz : integer := 09;constant dy : integer := 10;constant dx : integer := 11;
 
        constant f0     : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
 
        constant f6     : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
 
        constant s0     : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
 
        constant s6     : integer := 06;constant s7 : integer := 07;
 
        constant a0     : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;constant aa : integer := 03;
 
        constant p0     : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
 
 
 
        constant dpfifoab : integer := 00;
 
        constant dpfifocd : integer := 01;
 
 
 
 
 
 
 
 
 
 
 
        signal sparaminput                                      : vectorblock12;
 
        --!TBXSTART:FACTORS_N_ADDENDS
 
        signal sfactor                                          : vectorblock12;
 
        signal ssumando                                         : vectorblock08;
 
        signal sdpfifo_q                                        : vectorblock02;
 
        --!TBXEND
 
 
 
 
 
        --!TBXSTART:ARITHMETIC_RESULTS
 
        signal sresult                                          : vectorblock08;
 
        signal sprd32blk                                        : vectorblock06;
 
        signal sadd32blk                                        : vectorblock04;
 
        signal ssqr32blk,sinv32blk                      : xfloat32;
 
        signal snormfifo_q,snormfifo_d          : vectorblock03;
 
        --!TBXEND
 
 
 
 
 
        --!TBXSTART:SYNC_CHAIN
 
        signal ssync_chain                                      : std_logic_vector(25 downto 1);
 
        signal sres567w,sres123w,sres2w         : std_logic;
 
        signal sres0w,sres4w                            : std_logic;
 
        --!TBXEND
 
 
 
        --! Entradas
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