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--! @file ema32x2.vhd
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--! @file fadd32.vhd
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--! @brief RayTrac Floating Point Adder
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--! @brief RayTrac Floating Point Adder
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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--------------------------------------------------
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-- RAYTRAC (FP BRANCH)
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-- RAYTRAC (FP BRANCH)
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- ema32x2.vhd
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-- fadd32.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library lpm;
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use lpm.all;
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--! Esta entidad recibe dos números en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
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--! Esta entidad recibe dos números en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
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--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
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--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
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entity ema32x2 is
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entity fadd32 is
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port (
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port (
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clk,dpc : in std_logic;
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clk,dpc : in std_logic;
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a32,b32 : in std_logic_vector (31 downto 0);
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a32,b32 : in std_logic_vector (31 downto 0);
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c32 : out std_logic_vector(31 downto 0)
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c32 : out std_logic_vector(31 downto 0)
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);
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);
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end ema32x2;
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end fadd32;
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architecture ema32x2_arch of ema32x2 is
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architecture fadd32_arch of fadd32 is
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component lpm_mult
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component lpm_mult
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generic (
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generic (
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lpm_hint : string;
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lpm_hint : string;
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lpm_representation : string;
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lpm_representation : string;
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);
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);
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end component;
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end component;
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signal s1zero : std_logic;
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signal s1zero : std_logic;
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signal s1delta : std_logic_vector(5 downto 0);
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signal s1delta : std_logic_vector(5 downto 0);
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signal s0delta,s1exp,s2exp,s3exp,s4exp,s5exp,s5factor,s6exp,s6factor: std_logic_vector(7 downto 0);
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signal s0delta,s1exp,s2exp,s3exp,s4exp,s5exp,s6exp,s5factor,s6factor,s7exp,s7factor : std_logic_vector(7 downto 0);
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signal s1shifter,s5factorhot9 : std_logic_vector(8 downto 0);
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signal s1shifter,s5factorhot9,s6factorhot9 : std_logic_vector(8 downto 0);
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signal s1pl,s5pl : std_logic_vector(17 downto 0);
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signal s1pl,s6pl : std_logic_vector(17 downto 0);
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signal s5postshift,s6postshift : std_logic_vector(22 downto 0);
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signal s6postshift,s7postshift : std_logic_vector(22 downto 0);
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signal s1umantshift,s1umantfixed,s1postshift,s1xorslab,s2xorslab : std_logic_vector(23 downto 0);
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signal s1umantshift,s1umantfixed,s1postshift,s1xorslab,s2xorslab : std_logic_vector(23 downto 0);
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signal s2umantshift,s2mantfixed,s3mantfixed,s3mantshift,s4xorslab : std_logic_vector(24 downto 0);
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signal s2umantshift,s2mantfixed,s3mantfixed,s3mantshift,s4xorslab : std_logic_vector(24 downto 0);
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signal s5factorhot25 : std_logic_vector(24 downto 0);
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signal s5factorhot25 : std_logic_vector(24 downto 0);
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signal s4sresult,s5result,s6result : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s4sresult,s5result,s6result,s7result : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s1ph,s5ph : std_logic_vector(26 downto 0);
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signal s1ph,s6ph : std_logic_vector(26 downto 0);
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signal s0a,s0b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s0a,s0b : std_logic_vector(31 downto 0); -- Float 32 bit
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begin
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begin
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process (clk)
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process (clk)
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if (s0b(30 downto 23)&s0a(30 downto 23))=x"0000" then
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if (s0b(30 downto 23)&s0a(30 downto 23))=x"0000" then
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s1zero <= '0';
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s1zero <= '0';
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else
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else
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s1zero <= '1';
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s1zero <= '1';
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end if;
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end if;
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s1delta <= s0delta(7) & (s0delta(7) xor s0delta(4))&(s0delta(7) xor s0delta(4)) & s0delta(2 downto 0);
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s1delta <= s0delta(7) & (s0delta(7) xor s0delta(4))&(s0delta(7) xor s0delta(3)) & s0delta(2 downto 0);
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case s0delta(7) is
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case s0delta(7) is
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when '1' =>
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when '1' =>
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s1exp <= s0b(30 downto 23);
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s1exp <= s0b(30 downto 23);
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s1umantshift <= s0a(31)&s0a(22 downto 0);
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s1umantshift <= s0a(31)&s0a(22 downto 0);
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s1umantfixed <= s0b(31)&s0b(22 downto 0);
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s1umantfixed <= s0b(31)&s0b(22 downto 0);
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--! Etapa2: Signar la mantissa denormalizada.
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--! Etapa2: Signar la mantissa denormalizada.
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s3mantfixed <= s2mantfixed;
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s3mantfixed <= s2mantfixed;
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s3mantshift <= s2umantshift(24)& ( ( s2umantshift(23 downto 0) xor s2xorslab) + ( x"00000"&"000"&s2umantshift(24) ) );
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s3mantshift <= s2umantshift(24)& ( ( s2umantshift(23 downto 0) xor s2xorslab) + ( x"00000"&"000"&s2umantshift(24) ) );
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s3exp <= s2exp;
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s3exp <= s2exp;
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--! Etapa 3: Etapa 3 Realizar la suma, quitar el signo de la mantissa y codificar el corrimiento hacia la izquierda.
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--! Etapa 3: Etapa 3 Realizar la suma, entre la mantissa corrida y la fija.
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s4sresult <= (s3mantshift(24)&s3mantshift)+(s3mantfixed(24)&s3mantfixed);
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s4sresult <= (s3mantshift(24)&s3mantshift)+(s3mantfixed(24)&s3mantfixed);
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s4exp <= s3exp;
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s4exp <= s3exp;
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--! Etapa 4: Quitar el signo a la mantissa resultante.
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--! Etapa 4: Quitar el signo a la mantissa resultante.
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s5result <= s4sresult(25)&((s4sresult(24 downto 0) xor s4xorslab) +(x"000000"&s4sresult(25)));
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s5result <= s4sresult(25)&((s4sresult(24 downto 0) xor s4xorslab) +(x"000000"&s4sresult(25)));
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--! Etapa 5: Codificar el corrimiento para la normalizacion de la mantissa resultante.
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--! Etapa 5: Codificar el corrimiento para la normalizacion de la mantissa resultante.
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s6result <= s5result;
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s6result <= s5result;
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s6exp <= s5exp;
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s6exp <= s5exp;
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s6factor <= s5factor;
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s6factor <= s5factor;
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s6postshift <= s5postshift;
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s6factorhot9 <= s5factorhot9;
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--! Etapa 6: Entregar el resultado.
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--! Etapa 6: Ejecutar el corrimiento de la mantissa.
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c32(31) <= s6result(25);
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s7result <= s6result;
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c32(30 downto 23) <= s6exp+s6factor+x"ff";
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s7exp <= s6exp;
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case s6factor(4 downto 3) is
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s7factor <= s6factor+x"ff";
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when "01" => c32(22 downto 0) <= s6postshift(14 downto 00)&x"00";
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s7postshift <= s6postshift;
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when "10" => c32(22 downto 0) <= s6postshift(06 downto 00)&x"0000";
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when others => c32(22 downto 0) <= s6postshift;
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--! Etapa 7: Entregar el resultado.
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c32(31) <= s7result(25);
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c32(30 downto 23) <= s7exp+s7factor;
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case s7factor(4 downto 3) is
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when "01" => c32(22 downto 0) <= s7postshift(14 downto 00)&x"00";
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when "10" => c32(22 downto 0) <= s7postshift(06 downto 00)&x"0000";
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when others => c32(22 downto 0) <= s7postshift;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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--! Combinatorial gremlin, Etapa 0 el corrimiento de la mantissa con menor exponente y reorganiza los operandos,\n
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--! Combinatorial gremlin, Etapa 0 el corrimiento de la mantissa con menor exponente y reorganiza los operandos,\n
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--! si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene.
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--! si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene.
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--! Combinatorial Gremlin, Etapa 5: Codificar el factor de normalizacion de la mantissa resultante.
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--! Combinatorial Gremlin, Etapa 5: Codificar el factor de normalizacion de la mantissa resultante.
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normalizerdecodeshift:
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normalizerdecodeshift:
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process (s5result,s5factorhot25)
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process (s5result,s5factorhot25)
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begin
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begin
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s5factor<=(others => '0');
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s5factor <= x"00";
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s5factorhot25 <= (others => '0');
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s5factorhot25 <= '0'&x"000000";
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for i in 24 downto 0 loop
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for i in 24 downto 0 loop
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if s5result(i)='1' then
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if s5result(i)='1' then
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s5factor <= conv_std_logic_vector(24-i,8);
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s5factor <= conv_std_logic_vector(24-i,8);
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s5factorhot25(24-i) <= '1';
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s5factorhot25(24-i) <= '1';
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exit;
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exit;
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end if;
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end if;
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end loop;
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end loop;
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s5factorhot9 <= (s5factorhot25(8 downto 1)or s5factorhot25(16 downto 9)or s5factorhot25(24 downto 17)) & s5factorhot25(0);
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s5factorhot9 <= (s5factorhot25(8 downto 1)or s5factorhot25(16 downto 9)or s5factorhot25(24 downto 17)) & s5factorhot25(0);
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end process;
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end process;
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--! Etapa 6: Ejecutar el corrimiento para normalizar la mantissa.
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normhighshiftermult:lpm_mult
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normhighshiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,18,27)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,18,27)
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port map (s5factorhot9,s5result(24 downto 7),s5ph);
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port map (s6factorhot9,s6result(24 downto 7),s6ph);
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normlowshiftermult:lpm_mult
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normlowshiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (s5factorhot9,s5result(06 downto 0)&"00",s5pl);
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port map (s6factorhot9,s6result(06 downto 0)&"00",s6pl);
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s5postshift(22 downto 15) <= s5ph(16 downto 09);
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s6postshift(22 downto 15) <= s6ph(16 downto 09);
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s5postshift(14 downto 06) <= s5ph(08 downto 00); --! Activar este pedazo si se requiere extrema precision or s5pl(17 downto 9);
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s6postshift(14 downto 06) <= s6ph(08 downto 00); --! Activar este pedazo si se requiere extrema precision or s5pl(17 downto 9);
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s5postshift(05 downto 00) <= s5pl(08 downto 03);
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s6postshift(05 downto 00) <= s6pl(08 downto 03);
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end ema32x2_arch;
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end fadd32_arch;
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