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library lpm;
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library lpm;
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use lpm.all;
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use lpm.all;
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--! Esta entidad recibe dos números en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
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--! Esta entidad recibe dos números en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
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--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
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--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
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entity fadd32 is
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entity fadd32 is
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generic (
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propagation_chain : string := "ON"
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);
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port (
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port (
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clk,dpc,ena : in std_logic;
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clk,dpc,prop_in : in std_logic;
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a32,b32 : in std_logic_vector (31 downto 0);
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a32,b32 : in std_logic_vector (31 downto 0);
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c32 : out std_logic_vector(31 downto 0)
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c32,prop_out : out std_logic_vector(31 downto 0)
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);
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);
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end fadd32;
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end fadd32;
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architecture fadd32_arch of fadd32 is
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architecture fadd32_arch of fadd32 is
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component lpm_mult
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component lpm_mult
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signal s5factorhot24 : std_logic_vector(23 downto 0);
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signal s5factorhot24 : std_logic_vector(23 downto 0);
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signal s2umantshift,s2mantfixed,s3mantfixed,s3mantshift,s4xorslab : std_logic_vector(24 downto 0);
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signal s2umantshift,s2mantfixed,s3mantfixed,s3mantshift,s4xorslab : std_logic_vector(24 downto 0);
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signal s4sresult,s5result,s6result : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s4sresult,s5result,s6result : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s1ph,s6ph : std_logic_vector(26 downto 0);
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signal s1ph,s6ph : std_logic_vector(26 downto 0);
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signal s0a,s0b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s0a,s0b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal sxprop : std_logic_vector(7 downto 0);
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begin
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begin
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propagation:
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process (clk,ena)
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if propagation_chain="ON" generate
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prop_out <= sxprop(7);
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process (clk)
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begin
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if clk'event and clk='1' then
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for i in 7 downto 1 loop
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sxprop(i) <= sxprop(i-1);
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end loop;
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sxprop(0) <= prop_in;
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end if;
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end process;
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end generate propagation ;
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process (clk)
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begin
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begin
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if clk'event and clk='1' and ena='1' then
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if clk'event and clk='1' then
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--!Registro de entrada
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--!Registro de entrada
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s0a <= a32;
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s0a <= a32;
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(30 downto 0) <= b32(30 downto 0);
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s0b(30 downto 0) <= b32(30 downto 0);
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