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[/] [raytrac/] [branches/] [fp/] [fmul32.vhd] - Diff between revs 139 and 150
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Rev 150 |
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity fmul32 is
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entity fmul32 is
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generic (
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propagation_chain : string := "ON"
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);
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port (
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port (
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clk,prop_in : in std_logic;
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clk : in std_logic;
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a32,b32 : in std_logic_vector(31 downto 0);
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a32,b32 : in std_logic_vector(31 downto 0);
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p32,prop_out : out std_logic_vector(31 downto 0)
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p32 : out std_logic_vector(31 downto 0)
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);
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);
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end fmul32;
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end fmul32;
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architecture fmul32_arch of fmul32 is
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architecture fmul32_arch of fmul32 is
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signal s1ac,s1umu:std_logic_vector(35 downto 0);
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signal s1ac,s1umu:std_logic_vector(35 downto 0);
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signal s2umu:std_logic_vector(24 downto 0);
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signal s2umu:std_logic_vector(24 downto 0);
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signal sxprop : std_logic_vector(2 downto 0);
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signal sxprop : std_logic_vector(2 downto 0);
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begin
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begin
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propagation:
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if propagation_chain="ON" generate
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prop_out <= sxprop(2);
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process (clk)
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begin
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if clk'event and clk='1' then
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for i in 2 downto 1 loop
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sxprop(i) <= sxprop(i-1);
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end loop;
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sxprop(0) <= prop_in;
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end if;
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end process;
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end generate propagation ;
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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