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architecture fmul32_arch of fmul32 is
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architecture fmul32_arch of fmul32 is
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--Stage 0 signals
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--Stage 0 signals
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signal s0dataa_alfa,s0dataa_beta,s0dataa_gama,s0datab : std_logic_vector(17 downto 0);
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--!TBXSTART:MULT_STAGE0
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--!TBXSTART:MULT_STAGE0
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signal s0sga,s0sgb,s0zrs : std_logic;
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signal s0sga,s0sgb,s0zrs : std_logic;
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signal s0exp : std_logic_vector(7 downto 0);
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signal s0exp : std_logic_vector(7 downto 0);
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signal s0uma,s0umb : std_logic_vector(22 downto 0);
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signal s0uma,s0umb : std_logic_vector(22 downto 0);
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signal s0ac : std_logic_vector(35 downto 0);
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signal s0ac : std_logic_vector(35 downto 0);
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end process;
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end process;
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--! Combinatorial Gremlin Etapa 0 : multiplicacion de la mantissa, suma de los exponentes y multiplicación de los signos.
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--! Combinatorial Gremlin Etapa 0 : multiplicacion de la mantissa, suma de los exponentes y multiplicación de los signos.
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--! Multipliers
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--! Multipliers
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s0dataa_alfa <= s0zrs&s0uma(22 downto 6);
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s0datab <= s0zrs&s0umb(22 downto 6);
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mult18x18ac:lpm_mult
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mult18x18ac:lpm_mult
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generic map (
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 0,
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lpm_pipeline => 0,
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lpm_representation => "UNSIGNED",
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lpm_representation => "UNSIGNED",
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lpm_widtha => 18,
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lpm_widtha => 18,
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lpm_widthb => 18,
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lpm_widthb => 18,
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lpm_widthp => 36
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lpm_widthp => 36
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)
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)
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port map (
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port map (
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dataa => s0zrs&s0uma(22 downto 6),
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dataa => s0dataa_alfa,
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datab => s0zrs&s0umb(22 downto 6),
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datab => s0datab,
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result => s0ac
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result => s0ac
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);
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);
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s0dataa_beta <= s0zrs&s0uma(22 downto 6);
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mult18x6ad:lpm_mult
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mult18x6ad:lpm_mult
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generic map (
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 0,
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lpm_pipeline => 0,
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lpm_representation => "UNSIGNED",
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lpm_representation => "UNSIGNED",
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lpm_widtha => 18,
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lpm_widtha => 18,
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lpm_widthb => 6,
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lpm_widthb => 6,
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lpm_widthp => 24
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lpm_widthp => 24
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)
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)
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port map (
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port map (
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dataa => s0zrs&s0uma(22 downto 6),
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dataa => s0dataa_beta,
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datab => s0umb(5 downto 0),
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datab => s0umb(5 downto 0),
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result => s0ad
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result => s0ad
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);
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);
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s0dataa_gama <= s0zrs&s0umb(22 downto 6);
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mult18x6bc:lpm_mult
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mult18x6bc:lpm_mult
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generic map (
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 0,
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lpm_pipeline => 0,
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lpm_representation => "UNSIGNED",
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lpm_representation => "UNSIGNED",
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lpm_widtha => 18,
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lpm_widtha => 18,
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lpm_widthb => 6,
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lpm_widthb => 6,
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lpm_widthp => 24
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lpm_widthp => 24
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)
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)
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port map (
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port map (
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dataa => s0zrs&s0umb(22 downto 6),
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dataa => s0dataa_gama,
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datab => s0uma(5 downto 0),
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datab => s0uma(5 downto 0),
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result => s0bc
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result => s0bc
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);
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);
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--! Exponent Addition
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--! Exponent Addition
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