| Line 37... |
Line 37... |
);
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);
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port (
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port (
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clk,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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clk,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
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dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_rd,ext_wr,int_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad+widthadmemblock-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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ext_q : out std_logic_vector(width-1 downto 0);
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ext_q : out std_logic_vector(width-1 downto 0);
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| Line 150... |
Line 150... |
results_blocks:
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results_blocks:
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for i in 7 downto 0 generate
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for i in 7 downto 0 generate
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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resultsblock : altsyncram
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resultsblock : altsyncram
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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port map (ext_rd,clk,int_wr_add,ext_rd_add(widthadmemblock-1 downto 0),'1',s1ext_q(i),sint_d(i));
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port map (int_wr,clk,int_wr_add,ext_rd_add(widthadmemblock-1 downto 0),ext_rd,s1ext_q(i),sint_d(i));
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end generate results_blocks;
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end generate results_blocks;
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operands_blocks:
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operands_blocks:
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for i in 11 downto 0 generate
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for i in 11 downto 0 generate
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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operandsblock : altsyncram
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operandsblock : altsyncram
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add(i/6),'1',s1int_q(i),s0ext_d);
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port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
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end generate operands_blocks;
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end generate operands_blocks;
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operands_block_proc: process (clk)
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operands_block_proc: process (clk)
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begin
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begin
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