| Line 37... |
Line 37... |
);
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);
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port (
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port (
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clk,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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clk,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
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dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
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instrfifo_flush,instrfifo_rd,instrfifo_wr: in std_logic;
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instrfifo_empty,instrfifo_full : out std_logic;
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ext_rd,ext_wr,int_wr: in std_logic;
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ext_rd,ext_wr,int_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad+widthadmemblock-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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ext_q : out std_logic_vector(width-1 downto 0);
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ext_q : out std_logic_vector(width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_wr_add : in std_logic_vector(widthadmemblock-1 downto 0);
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int_wr_add : in std_logic_vector(widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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instrfifo_d : in std_logic_vector(width-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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);
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);
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| Line 141... |
Line 144... |
generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",9,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",9,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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normfifo : scfifo
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normfifo : scfifo
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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instrfifo : scififo
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE_M9K",64,"OFF","SCIFIFO",32,6,"OFF","OFF","ON")
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port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrifo_full);
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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results_blocks:
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results_blocks:
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