| Line 35... |
Line 35... |
external_readable_widthad : integer := 3;
|
external_readable_widthad : integer := 3;
|
external_writeable_widthad : integer := 4
|
external_writeable_widthad : integer := 4
|
);
|
);
|
port (
|
port (
|
|
|
clk,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
|
clk,ena,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
|
dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
|
dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
|
instrfifo_flush,instrfifo_rd,instrfifo_wr: in std_logic;
|
instrfifo_flush,instrfifo_rd,instrfifo_wr,resultfifo_flush,resultfifo_wr: in std_logic;
|
instrfifo_empty,instrfifo_full : out std_logic;
|
instrfifo_empty,instrfifo_full : out std_logic;
|
ext_rd,ext_wr,int_wr: in std_logic;
|
ext_rd,ext_wr: in std_logic;
|
ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
|
ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
|
ext_rd_add : in std_logic_vector(external_readable_widthad+widthadmemblock-1 downto 0);
|
ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
|
ext_d: in std_logic_vector(width-1 downto 0);
|
ext_d: in std_logic_vector(width-1 downto 0);
|
|
resultfifo_full,resultfifo_empty : out std_logic_vector(external_readable_blocks-1 downto 0);
|
int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
|
int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
|
ext_q : out std_logic_vector(width-1 downto 0);
|
ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
|
int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
|
int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
|
int_wr_add : in std_logic_vector(widthadmemblock-1 downto 0);
|
|
int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
|
int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
|
instrfifo_d : in std_logic_vector(width-1 downto 0);
|
instrfifo_d : in std_logic_vector(width-1 downto 0);
|
dpfifo_d : in std_logic_vector(width*2-1 downto 0);
|
dpfifo_d : in std_logic_vector(width*2-1 downto 0);
|
normfifo_d : in std_logic_vector(width*3-1 downto 0);
|
normfifo_d : in std_logic_vector(width*3-1 downto 0);
|
dpfifo_q : out std_logic_vector(width*2-1 downto 0);
|
dpfifo_q : out std_logic_vector(width*2-1 downto 0);
|
| Line 65... |
Line 65... |
type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
|
type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
|
|
|
component scfifo
|
component scfifo
|
generic (
|
generic (
|
add_ram_output_register :string;
|
add_ram_output_register :string;
|
|
almost_full_value :natural;
|
|
allow_wrcycle_when_full :string;
|
intended_device_family :string;
|
intended_device_family :string;
|
lpm_hint :string;
|
lpm_hint :string;
|
lpm_numwords :natural;
|
lpm_numwords :natural;
|
lpm_showahead :string;
|
lpm_showahead :string;
|
lpm_type :string;
|
lpm_type :string;
|
| Line 84... |
Line 86... |
empty : out std_logic;
|
empty : out std_logic;
|
clock : in std_logic;
|
clock : in std_logic;
|
q : out std_logic_vector(lpm_width-1 downto 0);
|
q : out std_logic_vector(lpm_width-1 downto 0);
|
wrreq : in std_logic;
|
wrreq : in std_logic;
|
data : in std_logic_vector(lpm_width-1 downto 0);
|
data : in std_logic_vector(lpm_width-1 downto 0);
|
|
almost_full : out std_logic;
|
full : out std_logic
|
full : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component altsyncram
|
component altsyncram
|
| Line 127... |
Line 130... |
end component;
|
end component;
|
signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1 downto 0);
|
signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1 downto 0);
|
signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
|
signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
|
signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
|
signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
|
signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
|
signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
|
signal s0int_wr_add : std_logic_vector(widthadmemblock-1 downto 0);
|
signal s0ext_wr,s0ext_rd : std_logic;
|
signal s0ext_wr : std_logic;
|
|
signal s0ext_d : std_logic_vector(width-1 downto 0);
|
signal s0ext_d : std_logic_vector(width-1 downto 0);
|
|
signal s0ext_rd_ack : std_logic_vector(external_readable_blocks-1 downto 0);
|
signal s1ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
|
signal s0ext_q,sint_d : vectorblock08;
|
signal s1ext_q,sint_d : vectorblock08;
|
|
signal sint_rd_add : vectorblock02;
|
signal sint_rd_add : vectorblock02;
|
signal s1int_q : vectorblock12;
|
signal s1int_q : vectorblock12;
|
|
|
begin
|
begin
|
|
|
dpfifo : scfifo --! Debe ir registrada la salida.
|
dpfifo : scfifo --! Debe ir registrada la salida.
|
generic map ("ON","Cyclone III","RAM_BLOCK_TYPE=M9K",15,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
|
generic map ("ON",9,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",16,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
|
port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
|
port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
|
normfifo : scfifo
|
normfifo : scfifo
|
generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
|
generic map ("ON",23,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",32,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
|
port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
|
port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
|
instrfifo : scififo
|
instrfifo : scfifo
|
generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE_M9K",64,"OFF","SCIFIFO",32,6,"OFF","OFF","ON")
|
generic map ("ON",31,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",32,"OFF","SCIFIFO",32,5,"ON","OFF","ON")
|
port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrifo_full);
|
port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrfifo_full);
|
|
|
|
|
sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
|
sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
|
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
|
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
|
|
|
results_blocks:
|
results_blocks:
|
for i in 7 downto 0 generate
|
for i in 7 downto 0 generate
|
sint_d(i) <= int_d((i+1)*width-1 downto i*width);
|
sint_d(i) <= int_d((i+1)*width-1 downto i*width);
|
resultsblock : altsyncram
|
resultsfifo : scfifo
|
generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
|
generic map ("ON",511,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",512,"OFF","SCIFIFO",32,9,"ON","OFF","ON")
|
port map (int_wr,clk,int_wr_add,ext_rd_add(widthadmemblock-1 downto 0),ext_rd,s1ext_q(i),sint_d(i));
|
port map (s0ext_rd_ack(i),resultfifo_flush,resultfifo_empty(i),clk,s0ext_q(i),resultfifo_wr,sint_d(i),open,resultfifo_full(i));
|
|
-- resultsblock : altsyncram
|
|
-- generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
|
|
-- port map (resultfifo_wr,clk,resultfifo_wr_add,ext_rd_add(widthadmemblock-1 downto 0),ext_rd,s1ext_q(i),sint_d(i));
|
end generate results_blocks;
|
end generate results_blocks;
|
|
|
operands_blocks:
|
operands_blocks:
|
for i in 11 downto 0 generate
|
for i in 11 downto 0 generate
|
int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
|
int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
|
| Line 169... |
Line 173... |
generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
|
generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
|
port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
|
port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
|
end generate operands_blocks;
|
end generate operands_blocks;
|
|
|
|
|
operands_block_proc: process (clk)
|
operands_block_proc: process (clk,ena)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' and ena='1' then
|
--! Registro de entrada
|
--! Registro de entrada
|
s0ext_wr_add <= ext_wr_add;
|
s0ext_wr_add <= ext_wr_add;
|
s0ext_wr <= ext_wr;
|
s0ext_wr <= ext_wr;
|
s0ext_d <= ext_d;
|
s0ext_d <= ext_d;
|
|
end if;
|
|
end process;
|
|
operands_block_comb: process (s0ext_wr_add,s0ext_wr)
|
|
begin
|
|
|
--! Etapa 0: Decodificacion de las señ:ales de escritura.
|
--! Etapa 0: Decodificacion de las señ:ales de escritura.
|
case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
|
case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
|
when x"0" => s0ext_wr_add_one_hot <= x"00"&"000"&s0ext_wr;
|
when x"0" => s0ext_wr_add_one_hot <= x"00"&"000"&s0ext_wr;
|
when x"1" => s0ext_wr_add_one_hot <= x"00"&"00"&s0ext_wr&'0';
|
when x"1" => s0ext_wr_add_one_hot <= x"00"&"00"&s0ext_wr&'0';
|
when x"2" => s0ext_wr_add_one_hot <= x"00"&'0'&s0ext_wr&"00";
|
when x"2" => s0ext_wr_add_one_hot <= x"00"&'0'&s0ext_wr&"00";
|
| Line 191... |
Line 200... |
when x"8" => s0ext_wr_add_one_hot <= "000"&s0ext_wr&x"00";
|
when x"8" => s0ext_wr_add_one_hot <= "000"&s0ext_wr&x"00";
|
when x"9" => s0ext_wr_add_one_hot <= "00"&s0ext_wr&'0'&x"00";
|
when x"9" => s0ext_wr_add_one_hot <= "00"&s0ext_wr&'0'&x"00";
|
when x"A" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"00"&x"00";
|
when x"A" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"00"&x"00";
|
when others => s0ext_wr_add_one_hot <= s0ext_wr&"000"&x"00";
|
when others => s0ext_wr_add_one_hot <= s0ext_wr&"000"&x"00";
|
end case;
|
end case;
|
end if;
|
|
end process;
|
end process;
|
results_block_proc: process(clk)
|
results_block_proc: process(clk,ena)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' and ena='1' then
|
--!Registrar entrada
|
--!Registrar entrada
|
s0ext_rd_add <= ext_rd_add(external_readable_widthad+widthadmemblock-1 downto widthadmemblock);
|
s0ext_rd_add <= ext_rd_add;
|
--!Etapa 0: Leer memorias
|
s0ext_rd <= ext_rd;
|
s1ext_rd_add <= s0ext_rd_add;
|
--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
|
--!Etapa 1: Seleccionar dato a leer;
|
case '0'&s0ext_rd_add is
|
case '0'&s1ext_rd_add is
|
when x"0" => ext_q <= s0ext_q(0);
|
when x"0" => ext_q <= s1ext_q(0);
|
when x"1" => ext_q <= s0ext_q(1);
|
when x"1" => ext_q <= s1ext_q(1);
|
when x"2" => ext_q <= s0ext_q(2);
|
when x"2" => ext_q <= s1ext_q(2);
|
when x"3" => ext_q <= s0ext_q(3);
|
when x"3" => ext_q <= s1ext_q(3);
|
when x"4" => ext_q <= s0ext_q(4);
|
when x"4" => ext_q <= s1ext_q(4);
|
when x"5" => ext_q <= s0ext_q(5);
|
when x"5" => ext_q <= s1ext_q(5);
|
when x"6" => ext_q <= s0ext_q(6);
|
when x"6" => ext_q <= s1ext_q(6);
|
when others => ext_q <= s0ext_q(7);
|
when others => ext_q <= s1ext_q(7);
|
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
|
|
begin
|
|
case '0'&s0ext_rd_add is
|
|
when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
|
|
when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
|
|
when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
|
|
when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
|
|
when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
|
|
when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
|
|
when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
|
|
when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
|
|
end case;
|
|
end process;
|
end memblock_arch;
|
end memblock_arch;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
