Line 126... |
Line 126... |
q_b : out std_logic_vector(width-1 downto 0);
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q_b : out std_logic_vector(width-1 downto 0);
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data_a : in std_logic_vector(width-1 downto 0)
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data_a : in std_logic_vector(width-1 downto 0)
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);
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);
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end component;
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end component;
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1 downto 0);
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0ext_wr,s0ext_rd : std_logic;
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signal s0ext_wr,s0ext_rd : std_logic;
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signal s0ext_d : std_logic_vector(width-1 downto 0);
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signal s0ext_d : std_logic_vector(width-1 downto 0);
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Line 139... |
Line 139... |
signal sint_rd_add : vectorblock02;
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signal sint_rd_add : vectorblock02;
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signal s1int_q : vectorblock12;
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signal s1int_q : vectorblock12;
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begin
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begin
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dpfifo : scfifo --! Debe ir registrada la salida.
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--! Cola interna de producto punto, ubicada entre el pipe line aritméco.
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generic map ("ON",9,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",16,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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q0q1 : scfifo --! Debe ir registrada la salida.
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generic map ("ON",8,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",16,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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normfifo : scfifo
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--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmé
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qxqyqz : scfifo
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generic map ("ON",23,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",32,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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generic map ("ON",23,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",32,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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instrfifo : scfifo
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--! Cola de instrucciones
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qi : scfifo
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generic map ("ON",31,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",32,"OFF","SCIFIFO",32,5,"ON","OFF","ON")
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generic map ("ON",31,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",32,"OFF","SCIFIFO",32,5,"ON","OFF","ON")
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port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrfifo_full);
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port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrfifo_full);
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--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracció:n de código, no influye en la sintesis del circuito.
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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--! Instanciación de la cola de resultados.
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results_blocks:
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results_blocks:
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for i in 7 downto 0 generate
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for i in 7 downto 0 generate
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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resultsfifo : scfifo
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resultsfifo : scfifo
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generic map ("ON",511,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",512,"OFF","SCIFIFO",32,9,"ON","OFF","ON")
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generic map ("ON",511,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",512,"OFF","SCIFIFO",32,9,"ON","OFF","ON")
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port map (s0ext_rd_ack(i),resultfifo_flush,resultfifo_empty(i),clk,s0ext_q(i),resultfifo_wr,sint_d(i),open,resultfifo_full(i));
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port map (s0ext_rd_ack(i),resultfifo_flush,resultfifo_empty(i),clk,s0ext_q(i),resultfifo_wr,sint_d(i),open,resultfifo_full(i));
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-- resultsblock : altsyncram
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-- generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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-- port map (resultfifo_wr,clk,resultfifo_wr_add,ext_rd_add(widthadmemblock-1 downto 0),ext_rd,s1ext_q(i),sint_d(i));
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end generate results_blocks;
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end generate results_blocks;
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--! Instanciación de la cola de resultados de salida.
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operands_blocks:
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operands_blocks:
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for i in 11 downto 0 generate
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for i in 11 downto 0 generate
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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operandsblock : altsyncram
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operandsblock : altsyncram
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
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port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
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end generate operands_blocks;
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end generate operands_blocks;
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--! Escritura en registros de operandos de entrada.
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operands_block_proc: process (clk,ena)
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operands_block_proc: process (clk,ena)
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begin
|
begin
|
if clk'event and clk='1' and ena='1' then
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if clk'event and clk='1' and ena='1' then
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--! Registro de entrada
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--! Registro de entrada
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s0ext_wr_add <= ext_wr_add;
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s0ext_wr_add <= ext_wr_add;
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s0ext_wr <= ext_wr;
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s0ext_wr <= ext_wr;
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s0ext_d <= ext_d;
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s0ext_d <= ext_d;
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end if;
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end if;
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end process;
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end process;
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--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.
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operands_block_comb: process (s0ext_wr_add,s0ext_wr)
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operands_block_comb: process (s0ext_wr_add,s0ext_wr)
|
begin
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begin
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--! Etapa 0: Decodificacion de las señ:ales de escritura.
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--! Etapa 0: Decodificacion de las señ:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.
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case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
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case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
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when x"0" => s0ext_wr_add_one_hot <= x"00"&"000"&s0ext_wr;
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when x"0" => s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
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when x"1" => s0ext_wr_add_one_hot <= x"00"&"00"&s0ext_wr&'0';
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when x"1" => s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
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when x"2" => s0ext_wr_add_one_hot <= x"00"&'0'&s0ext_wr&"00";
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when x"2" => s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
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when x"3" => s0ext_wr_add_one_hot <= x"00"&s0ext_wr&"000";
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when x"4" => s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
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when x"4" => s0ext_wr_add_one_hot <= x"0"&"000"&s0ext_wr&x"0";
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when x"5" => s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
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when x"5" => s0ext_wr_add_one_hot <= x"0"&"00"&s0ext_wr&'0'&x"0";
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when x"6" => s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
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when x"6" => s0ext_wr_add_one_hot <= x"0"&'0'&s0ext_wr&"00"&x"0";
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when x"8" => s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
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when x"7" => s0ext_wr_add_one_hot <= x"0"&s0ext_wr&"000"&x"0";
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when x"9" => s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
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when x"8" => s0ext_wr_add_one_hot <= "000"&s0ext_wr&x"00";
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when x"A" => s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
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when x"9" => s0ext_wr_add_one_hot <= "00"&s0ext_wr&'0'&x"00";
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when x"C" => s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
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when x"A" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"00"&x"00";
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when x"D" => s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
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when others => s0ext_wr_add_one_hot <= s0ext_wr&"000"&x"00";
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when x"E" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
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when others => s0ext_wr_add_one_hot <= '1'&x"000";
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end case;
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end case;
|
|
|
end process;
|
end process;
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|
|
|
--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.
|
results_block_proc: process(clk,ena)
|
results_block_proc: process(clk,ena)
|
begin
|
begin
|
if clk'event and clk='1' and ena='1' then
|
if clk'event and clk='1' and ena='1' then
|
--!Registrar entrada
|
--!Registrar entrada
|
s0ext_rd_add <= ext_rd_add;
|
s0ext_rd_add <= ext_rd_add;
|
Line 221... |
Line 230... |
when x"6" => ext_q <= s0ext_q(6);
|
when x"6" => ext_q <= s0ext_q(6);
|
when others => ext_q <= s0ext_q(7);
|
when others => ext_q <= s0ext_q(7);
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
--! rdack decoder para las colas de resultados de salida.
|
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
|
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
|
begin
|
begin
|
case '0'&s0ext_rd_add is
|
case '0'&s0ext_rd_add is
|
when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
|
when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
|
when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
|
when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
|