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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.arithpack.all;
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entity memblock is
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entity memblock is
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generic (
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generic (
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width : integer := 32;
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width : integer := 32;
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architecture memblock_arch of memblock is
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architecture memblock_arch of memblock is
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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constant rstMasterValue : std_logic := '0';
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component scfifo
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generic (
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add_ram_output_register :string;
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almost_full_value :natural;
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allow_wrcycle_when_full :string;
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intended_device_family :string;
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lpm_hint :string;
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lpm_numwords :natural;
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lpm_showahead :string;
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lpm_type :string;
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lpm_width :natural;
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lpm_widthu :natural;
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overflow_checking :string;
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underflow_checking :string;
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use_eab :string
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);
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port(
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rdreq : in std_logic;
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aclr : in std_logic;
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empty : out std_logic;
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clock : in std_logic;
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q : out std_logic_vector(lpm_width-1 downto 0);
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wrreq : in std_logic;
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data : in std_logic_vector(lpm_width-1 downto 0);
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almost_full : out std_logic;
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full : out std_logic
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);
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end component;
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component altsyncram
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generic (
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address_aclr_b : string;
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address_reg_b : string;
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clock_enable_input_a : string;
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clock_enable_input_b : string;
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clock_enable_output_b : string;
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intended_device_family : string;
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lpm_type : string;
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numwords_a : natural;
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numwords_b : natural;
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operation_mode : string;
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outdata_aclr_b : string;
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outdata_reg_b : string;
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power_up_uninitialized : string;
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ram_block_type : string;
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rdcontrol_reg_b : string;
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read_during_write_mode_mixed_ports : string;
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widthad_a : natural;
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widthad_b : natural;
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width_a : natural;
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width_b : natural;
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width_byteena_a : natural
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);
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port (
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wren_a : in std_logic;
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clock0 : in std_logic;
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address_a : in std_logic_vector(widthad_a-1 downto 0);
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address_b : in std_logic_vector(widthad_b-1 downto 0);
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rden_b : in std_logic;
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q_b : out std_logic_vector(width-1 downto 0);
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data_a : in std_logic_vector(width-1 downto 0)
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);
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end component;
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0ext_wr,s0ext_rd : std_logic;
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signal s0ext_wr,s0ext_rd : std_logic;
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