| Line 25... |
Line 25... |
use work.arithpack.all;
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use work.arithpack.all;
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entity memblock is
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entity memblock is
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generic (
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generic (
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width : integer := 32;
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blocksize : integer := 512;
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blocksize : integer := 512;
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widthadmemblock : integer :=9;
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external_writeable_blocks : integer := 12;
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external_writeable_blocks : integer := 12;
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external_readable_blocks : integer := 8;
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external_readable_blocks : integer := 8;
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external_readable_widthad : integer := 3;
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external_readable_widthad : integer := 3;
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external_writeable_widthad : integer := 4
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external_writeable_widthad : integer := 4
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);
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);
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| Line 42... |
Line 41... |
resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
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resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
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instrfifo_empty: out std_logic;
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instrfifo_empty: out std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*floatwidth-1 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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--!Python
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ext_q,instr fifo_q : out std_logic_vector(floatwidth-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*floatwidth-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
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);
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);
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end memblock;
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end memblock;
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architecture memblock_arch of memblock is
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architecture memblock_arch of memblock is
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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--!TBXSTART:MEMBLOCK_EXTERNAL_WRITE
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_wr : std_logic;
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signal s0ext_d : std_logic_vector(floatwidth-1 downto 0);
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--!TBXEND
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--!TBXSTART:MEMBLOCK_EXTERNAL_READ
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0ext_rd : std_logic;
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signal s0ext_wr,s0ext_rd : std_logic;
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signal s0ext_d : std_logic_vector(width-1 downto 0);
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signal s0ext_rd_ack : std_logic_vector(external_readable_blocks-1 downto 0);
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signal s0ext_rd_ack : std_logic_vector(external_readable_blocks-1 downto 0);
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signal s0ext_q,sint_d : vectorblock08;
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signal s0ext_q : vectorblock08;
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signal sint_rd_add : vectorblock02;
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--!TBXEND
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--!TBXSTART:MEMBLOCK_INTERNAL_READ
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal sint_rd_add : vectorblockadd02;
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signal s1int_q : vectorblock12;
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signal s1int_q : vectorblock12;
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--!TBXEND
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--!TBXSTART:MEMBLOCK_INTERNAL_WRITE
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signal sint_d : vectorblock08;
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signal sresultfifo_full : std_logic_vector(7 downto 0);
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signal sresultfifo_full : std_logic_vector(7 downto 0);
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--!TBXEND
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begin
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begin
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--! Cola interna de producto punto, ubicada entre el pipe line aritméco.
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--! Cola interna de producto cccccpunto, ubicada entre el pipe line aritméco.
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q0q1 : scfifo --! Debe ir registrada la salida.
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q0q1 : scfifo --! Debe ir registrada la salida.
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generic map (
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generic map (
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add_ram_output_register => "OFF",
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add_ram_output_register => "OFF",
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allow_wrcycle_when_full => "OFF",
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allow_wrcycle_when_full => "OFF",
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intended_device_family => "CycloneIII",
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intended_device_family => "CycloneIII",
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| Line 105... |
Line 116... |
q => dpfifo_q,
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q => dpfifo_q,
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wrreq => dpfifo_wr,
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wrreq => dpfifo_wr,
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data => dpfifo_d
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data => dpfifo_d
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);
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);
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--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmé
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--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmético
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qxqyqz : scfifo
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qxqyqz : scfifo
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generic map (
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generic map (
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add_ram_output_register => "OFF",
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add_ram_output_register => "OFF",
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allow_wrcycle_when_full => "OFF",
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allow_wrcycle_when_full => "OFF",
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intended_device_family => "Cyclone III",
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intended_device_family => "Cyclone III",
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| Line 169... |
Line 180... |
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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--! Instanciación de la cola de resultados de salida.
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--! Instanciación de la cola de resultados de salida.
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operands_blocks:
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operands_blocks:
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for i in 11 downto 0 generate
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for i in 11 downto 0 generate
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
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operandsblock : altsyncram
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operandsblock : altsyncram
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generic map (
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generic map (
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address_aclr_b => "NONE",
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address_aclr_b => "NONE",
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address_reg_b => "CLOCK0",
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address_reg_b => "CLOCK0",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_a => "BYPASS",
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| Line 190... |
Line 201... |
ram_block_type => "M9K",
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ram_block_type => "M9K",
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rdcontrol_reg_b => "CLOCK0",
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rdcontrol_reg_b => "CLOCK0",
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read_during_write_mode_mixed_ports => "OLD_DATA",
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read_during_write_mode_mixed_ports => "OLD_DATA",
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widthad_a => widthadmemblock,
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widthad_a => widthadmemblock,
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widthad_b => widthadmemblock,
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widthad_b => widthadmemblock,
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width_a => width,
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width_a => floatwidth,
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width_b => width,
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width_b => floatwidth,
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width_byteena_a => 1
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width_byteena_a => 1
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)
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)
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port map (
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port map (
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wren_a => s0ext_wr_add_one_hot(i),
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wren_a => s0ext_wr_add_one_hot(i),
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clock0 => clk,
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clock0 => clk,
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| Line 212... |
Line 223... |
resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
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resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
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resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
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resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
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resultfifo_full(0) <= sresultfifo_full(0);
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resultfifo_full(0) <= sresultfifo_full(0);
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results_blocks:
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results_blocks:
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for i in 7 downto 0 generate
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for i in 7 downto 0 generate
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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sint_d(i) <= int_d((i+1)*floatwidth-1 downto i*floatwidth);
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resultsfifo : scfifo
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resultsfifo : scfifo
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generic map (
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generic map (
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add_ram_output_register => "OFF",
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add_ram_output_register => "OFF",
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almost_full_value => 480,
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almost_full_value => 480,
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allow_wrcycle_when_full => "OFF",
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allow_wrcycle_when_full => "OFF",
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