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[/] [raytrac/] [branches/] [fp/] [memblock.vhd] - Diff between revs 157 and 158

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Rev 157 Rev 158
Line 27... Line 27... 
entity memblock is
 
entity memblock is
 
        generic (
 
        generic (
 
 
 
 
 
                blocksize : integer := 512;
 
                blocksize : integer := 512;
 
 
 
 
 
                external_writeable_blocks : integer := 12;
 
 
 
                external_readable_blocks  : integer := 8;
 
 
 
                external_readable_widthad       : integer := 3;
 
                external_readable_widthad       : integer := 3;
 
                external_writeable_widthad      : integer := 4
 
                external_writeable_widthad      : integer := 4
 
        );
 
        );
 
        port (
 
        port (
 
 
 
 
 
                clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
 
                clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
 
                instrfifo_rd : in std_logic;
 
                instrfifo_rd : in std_logic;
 
                resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
 
                resultfifo_wr: in std_logic_vector(8-1 downto 0);
 
                instrfifo_empty: out std_logic;
 
                instrfifo_empty: out std_logic;
 
                ext_rd,ext_wr: in std_logic;
 
                ext_rd,ext_wr: in std_logic;
 
                ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
 
                ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
 
                ext_rd_add : in std_logic_vector(2 downto 0);
 
                ext_rd_add : in std_logic_vector(2 downto 0);
 
                ext_d: in std_logic_vector(floatwidth-1 downto 0);
 
                ext_d: in std_logic_vector(floatwidth-1 downto 0);
 
                resultfifo_full  : out std_logic_vector(3 downto 0);
 
                resultfifo_full  : out std_logic_vector(3 downto 0);
 
                int_d : in std_logic_vector(external_readable_blocks*floatwidth-1 downto 0);
 
                int_d : in vectorblock08;
 
 
 
 
 
                --!Python
 
                --!Python
 
                ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
 
                ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
 
                int_q : out std_logic_vector(external_writeable_blocks*floatwidth-1 downto 0);
 
                int_q : out vectorblock12;
 
                int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
 
                int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
 
                dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
 
                dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
 
                normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
 
                normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
 
                dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
 
                dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
 
                normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
 
                normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
Line 63... Line 61... 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
        --!TBXSTART:MEMBLOCK_EXTERNAL_WRITE
 
        --!TBXSTART:MEMBLOCK_EXTERNAL_WRITE
 
        signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La señal extra es para la escritura de la cola de instrucciones.
 
        signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La señal extra es para la escritura de la cola de instrucciones.
 
        signal s0ext_wr_add                     : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
 
        signal s0ext_wr_add                     : std_logic_vector(4+widthadmemblock-1 downto 0);
 
        signal s0ext_wr                         : std_logic;
 
        signal s0ext_wr                         : std_logic;
 
        signal s0ext_d                          : std_logic_vector(floatwidth-1 downto 0);
 
        signal s0ext_d                          : std_logic_vector(floatwidth-1 downto 0);
 
        --!TBXEND
 
        --!TBXEND
 
        --! Señal de soporte
 
        --! Señal de soporte
 
        signal s0ext_wr_add_choice      : std_logic_vector(3 downto 0);
 
        signal s0ext_wr_add_choice      : std_logic_vector(3 downto 0);
 
 
 
 
 
        --!TBXSTART:MEMBLOCK_EXTERNAL_READ
 
        --!TBXSTART:MEMBLOCK_EXTERNAL_READ
 
        signal s0ext_rd_add                     : std_logic_vector(2 downto 0);
 
        signal s0ext_rd_add                     : std_logic_vector(2 downto 0);
 
        signal s0ext_rd                         : std_logic;
 
        signal s0ext_rd                         : std_logic;
 
        signal s0ext_rd_ack                     : std_logic_vector(external_readable_blocks-1 downto 0);
 
        signal s0ext_rd_ack                     : std_logic_vector(8-1 downto 0);
 
        signal s0ext_q                          : vectorblock08;
 
        signal s0ext_q                          : vectorblock08;
 
        --!TBXEND
 
        --!TBXEND
 
        --! Señal de soporte
 
        --! Señal de soporte
 
        signal s0ext_rd_add_choice      : std_logic_vector(3 downto 0);
 
        signal s0ext_rd_add_choice      : std_logic_vector(3 downto 0);
 
 
 
 
Line 183... Line 181... 
        --! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de código, no influye en la sintesis del circuito.
 
        --! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de código, no influye en la sintesis del circuito.
 
        sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
 
        sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
 
        sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
 
        sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
 
 
 
 
 
        --! Instanciaci&oacute;n de la cola de resultados de salida.
 
        --! Instanciaci&oacute;n de la cola de resultados de salida.
 
 
 
        int_q <= s1int_q;
 
        operands_blocks:
 
        operands_blocks:
 
        for i in 11 downto 0 generate
 
        for i in 11 downto 0 generate
 
                int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
 
                --!int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
 
                operandsblock : altsyncram
 
                operandsblock : altsyncram
 
                generic map (
 
                generic map (
 
                        address_aclr_b                                          => "NONE",
 
                        address_aclr_b                                          => "NONE",
 
                        address_reg_b                                           => "CLOCK0",
 
                        address_reg_b                                           => "CLOCK0",
 
                        clock_enable_input_a                            => "BYPASS",
 
                        clock_enable_input_a                            => "BYPASS",
Line 226... Line 225... 
        --! Instanciaci&oacute;n de la cola de resultados.
 
        --! Instanciaci&oacute;n de la cola de resultados.
 
        resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
 
        resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
 
        resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
 
        resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
 
        resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
 
        resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
 
        resultfifo_full(0) <= sresultfifo_full(0);
 
        resultfifo_full(0) <= sresultfifo_full(0);
 
 
 
        sint_d <= int_d;
 
        results_blocks:
 
        results_blocks:
 
        for i in 7 downto 0 generate
 
        for i in 7 downto 0 generate
 
                sint_d(i) <= int_d((i+1)*floatwidth-1 downto i*floatwidth);
 
 
 
                resultsfifo : scfifo
 
                resultsfifo : scfifo
 
                generic map     (
 
                generic map     (
 
                        add_ram_output_register => "OFF",
 
                        add_ram_output_register => "OFF",
 
                        almost_full_value               => 480,
 
                        almost_full_value               => 480,
 
                        allow_wrcycle_when_full => "OFF",
 
                        allow_wrcycle_when_full => "OFF",
Line 274... Line 273... 
                        s0ext_d  <= ext_d;
 
                        s0ext_d  <= ext_d;
 
                end if;
 
                end if;
 
        end process;
 
        end process;
 
 
 
 
 
        --! Decodificaci&oacute;n de se&ntilde;al escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la direcci&oacute;n de entrada.
 
        --! Decodificaci&oacute;n de se&ntilde;al escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la direcci&oacute;n de entrada.
 
        s0ext_wr_add_choice <= s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock);
 
        s0ext_wr_add_choice <= s0ext_wr_add(4+widthadmemblock-1 downto widthadmemblock);
 
        operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)
 
        operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)
 
        begin
 
        begin
 
 
 
 
 
                --! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como est&aacute; el pool de direcciones por bloques de vectores.
 
                --! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como est&aacute; el pool de direcciones por bloques de vectores.
 
                --! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
 
                --! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.

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