Line 27... |
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entity memblock is
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entity memblock is
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generic (
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generic (
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blocksize : integer := 512;
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blocksize : integer := 512;
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external_writeable_blocks : integer := 12;
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external_readable_blocks : integer := 8;
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external_readable_widthad : integer := 3;
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external_readable_widthad : integer := 3;
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external_writeable_widthad : integer := 4
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external_writeable_widthad : integer := 4
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);
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);
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port (
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port (
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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instrfifo_rd : in std_logic;
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instrfifo_rd : in std_logic;
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resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
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resultfifo_wr: in std_logic_vector(8-1 downto 0);
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instrfifo_empty: out std_logic;
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instrfifo_empty: out std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(2 downto 0);
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ext_rd_add : in std_logic_vector(2 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*floatwidth-1 downto 0);
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int_d : in vectorblock08;
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--!Python
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--!Python
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*floatwidth-1 downto 0);
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int_q : out vectorblock12;
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
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dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
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normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
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Line 63... |
Line 61... |
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--!TBXSTART:MEMBLOCK_EXTERNAL_WRITE
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--!TBXSTART:MEMBLOCK_EXTERNAL_WRITE
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La señal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La señal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_wr_add : std_logic_vector(4+widthadmemblock-1 downto 0);
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signal s0ext_wr : std_logic;
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signal s0ext_wr : std_logic;
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signal s0ext_d : std_logic_vector(floatwidth-1 downto 0);
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signal s0ext_d : std_logic_vector(floatwidth-1 downto 0);
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--!TBXEND
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--!TBXEND
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--! Señal de soporte
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--! Señal de soporte
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signal s0ext_wr_add_choice : std_logic_vector(3 downto 0);
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signal s0ext_wr_add_choice : std_logic_vector(3 downto 0);
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--!TBXSTART:MEMBLOCK_EXTERNAL_READ
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--!TBXSTART:MEMBLOCK_EXTERNAL_READ
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signal s0ext_rd_add : std_logic_vector(2 downto 0);
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signal s0ext_rd_add : std_logic_vector(2 downto 0);
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signal s0ext_rd : std_logic;
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signal s0ext_rd : std_logic;
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signal s0ext_rd_ack : std_logic_vector(external_readable_blocks-1 downto 0);
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signal s0ext_rd_ack : std_logic_vector(8-1 downto 0);
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signal s0ext_q : vectorblock08;
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signal s0ext_q : vectorblock08;
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--!TBXEND
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--!TBXEND
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--! Señal de soporte
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--! Señal de soporte
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signal s0ext_rd_add_choice : std_logic_vector(3 downto 0);
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signal s0ext_rd_add_choice : std_logic_vector(3 downto 0);
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--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracció:n de código, no influye en la sintesis del circuito.
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--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracció:n de código, no influye en la sintesis del circuito.
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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--! Instanciación de la cola de resultados de salida.
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--! Instanciación de la cola de resultados de salida.
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int_q <= s1int_q;
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operands_blocks:
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operands_blocks:
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for i in 11 downto 0 generate
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for i in 11 downto 0 generate
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int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
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--!int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
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operandsblock : altsyncram
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operandsblock : altsyncram
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generic map (
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generic map (
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address_aclr_b => "NONE",
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address_aclr_b => "NONE",
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address_reg_b => "CLOCK0",
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address_reg_b => "CLOCK0",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_a => "BYPASS",
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Line 226... |
Line 225... |
--! Instanciación de la cola de resultados.
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--! Instanciación de la cola de resultados.
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resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
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resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
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resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
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resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
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resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
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resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
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resultfifo_full(0) <= sresultfifo_full(0);
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resultfifo_full(0) <= sresultfifo_full(0);
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sint_d <= int_d;
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results_blocks:
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results_blocks:
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for i in 7 downto 0 generate
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for i in 7 downto 0 generate
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sint_d(i) <= int_d((i+1)*floatwidth-1 downto i*floatwidth);
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resultsfifo : scfifo
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resultsfifo : scfifo
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generic map (
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generic map (
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add_ram_output_register => "OFF",
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add_ram_output_register => "OFF",
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almost_full_value => 480,
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almost_full_value => 480,
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allow_wrcycle_when_full => "OFF",
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allow_wrcycle_when_full => "OFF",
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Line 274... |
Line 273... |
s0ext_d <= ext_d;
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s0ext_d <= ext_d;
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end if;
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end if;
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end process;
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end process;
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--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.
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--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.
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s0ext_wr_add_choice <= s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock);
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s0ext_wr_add_choice <= s0ext_wr_add(4+widthadmemblock-1 downto widthadmemblock);
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operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)
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operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)
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begin
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begin
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--! Etapa 0: Decodificacion de las señ:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.
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--! Etapa 0: Decodificacion de las señ:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.
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--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
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--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
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