| Line 38... |
Line 38... |
instrfifo_rd : in std_logic;
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instrfifo_rd : in std_logic;
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resultfifo_wr: in std_logic_vector(8-1 downto 0);
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resultfifo_wr: in std_logic_vector(8-1 downto 0);
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instrfifo_empty: out std_logic;
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instrfifo_empty: out std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(2 downto 0);
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ext_rd_add : in std_logic_vector(3 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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int_d : in vectorblock08;
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int_d : in vectorblock08;
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--!Python
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status_register : in std_logic_vector(3 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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int_q : out vectorblock12;
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int_q : out vectorblock12;
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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| Line 70... |
Line 71... |
--!TBXEND
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--!TBXEND
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--! Señal de soporte
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--! Señal de soporte
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signal s0ext_wr_add_choice : std_logic_vector(3 downto 0);
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signal s0ext_wr_add_choice : std_logic_vector(3 downto 0);
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--!TXBXSTART:MEMBLOCK_EXTERNAL_READ
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--!TXBXSTART:MEMBLOCK_EXTERNAL_READ
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signal s0ext_rd_add : std_logic_vector(2 downto 0);
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signal s0status_register : std_logic_vector(7 downto 0);
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signal s0ext_rd_add : std_logic_vector(3 downto 0);
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signal s0ext_rd : std_logic;
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signal s0ext_rd : std_logic;
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signal s0ext_rd_ack : std_logic_vector(8-1 downto 0);
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signal s0ext_rd_ack : std_logic_vector(8-1 downto 0);
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signal s0ext_q : vectorblock08;
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signal s0ext_q : vectorblock08;
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--!TBXEND
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--!TBXEND
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--! Señal de soporte
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signal s0ext_rd_add_choice : std_logic_vector(3 downto 0);
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--!TBXSTART:MEMBLOCK_INTERNAL_READ
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--!TBXSTART:MEMBLOCK_INTERNAL_READ
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signal sint_rd_add : vectorblockadd02;
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signal sint_rd_add : vectorblockadd02;
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signal s1int_q : vectorblock12;
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signal s1int_q : vectorblock12;
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| Line 91... |
Line 91... |
signal sresultfifo_full : std_logic_vector(7 downto 0);
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signal sresultfifo_full : std_logic_vector(7 downto 0);
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--!TBXEND
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--!TBXEND
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begin
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begin
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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q0q1 : scfifo --! Debe ir registrada la salida.
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q0q1 : scfifo --! Debe ir registrada la salida.
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generic map (
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generic map (
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add_ram_output_register => "OFF",
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add_ram_output_register => "OFF",
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allow_rwcycle_when_full => "OFF",
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allow_rwcycle_when_full => "OFF",
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| Line 310... |
Line 314... |
end case;
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end case;
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end process;
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end process;
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--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.
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--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.
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s0ext_rd_add_choice <= '0'&s0ext_rd_add;
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results_block_proc: process(clk,rst)
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results_block_proc: process(clk,rst)
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begin
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begin
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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s0ext_rd_add <= (others => '0');
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s0ext_rd_add <= (others => '0');
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s0ext_rd <= '0';
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s0ext_rd <= '0';
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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--!Registrar entrada
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--!Registrar entrada
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s0ext_rd_add <= ext_rd_add;
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s0ext_rd_add <= ext_rd_add;
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s0ext_rd <= ext_rd;
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s0ext_rd <= ext_rd;
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--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
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--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
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case s0ext_rd_add_choice is
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case s0ext_rd_add is
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when x"0" => ext_q <= s0ext_q(0);
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when x"0" => ext_q <= s0ext_q(0);
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when x"1" => ext_q <= s0ext_q(1);
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when x"1" => ext_q <= s0ext_q(1);
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when x"2" => ext_q <= s0ext_q(2);
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when x"2" => ext_q <= s0ext_q(2);
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when x"3" => ext_q <= s0ext_q(3);
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when x"3" => ext_q <= s0ext_q(3);
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when x"4" => ext_q <= s0ext_q(4);
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when x"4" => ext_q <= s0ext_q(4);
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when x"5" => ext_q <= s0ext_q(5);
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when x"5" => ext_q <= s0ext_q(5);
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when x"6" => ext_q <= s0ext_q(6);
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when x"6" => ext_q <= s0ext_q(6);
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when others => ext_q <= s0ext_q(7);
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when x"7" => ext_q <= s0ext_q(7);
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when others => ext_q <= x"000000"&s0status_register;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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--! rdack decoder para las colas de resultados de salida.
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--! rdack decoder para las colas de resultados de salida.
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results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add_choice)
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results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
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begin
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begin
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case s0ext_rd_add_choice is
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case s0ext_rd_add(3 downto 0) is
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when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
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when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
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when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
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when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
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when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
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when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
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when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
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when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
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when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
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when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
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when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
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when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
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when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
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when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
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when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
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when x"7" => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
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when others => s0ext_rd_ack <= (others => '0');
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end case;
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end case;
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end process;
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end process;
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--!Proceso para escribir el status register.
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--!Independiente del valor rfull(i) o si se lee o no, los bits correspondientes a los eventos de cola de resultados llena, se escriben reloj a reloj.
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--!Final de Instrucción: Si ocurre un evento de final de instrucción se escribe el bit de registro correspondiente.
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--!Si no hay un evento de final de instrucción entonces se verifica si hay un evento de lectura del status register, si es asi todos los bits correspondientes dentro del registro al evento de fin de instrucción se borran y quedan en cero.
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--!Si no hay un evento de final de instrucci&oacite;n y tampoco de lectura del status register entonces se deja el mismo valor del estatus register.
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sreg_proc: process (clk,rst,s0ext_rd_add,status_register(3 downto 0))
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begin
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if rst=rstMasterValue then
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s0status_register(7 downto 0) <= (others => '0');
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elsif clk'event and clk='1' then
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--!Sin importar el valor de las señales de cola de resultados llena, escribir el registro.
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s0status_register(7) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
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s0status_register(6) <= sresultfifo_full(4) or sresultfifo_full(2);
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s0status_register(5) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
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s0status_register(4) <= sresultfifo_full(0);
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for i in 3 downto 0 loop
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--! Si hay evento de fin de instrucción entonces escribir en el bit correspondiente un uno.
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if status_register(i)='1' then
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s0status_register(i) <= '1';
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--! Como no hubo final de instrucción revisar si hay lectura de Status Register y borrarlo.
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elsif s0ext_rd_add(3)='1' then
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s0status_register(i) <= '0';
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--! No ocurrio nada de lo anterior, dejar entonces en el mismo valor el Status Register.
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else
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s0status_register(i) <= s0status_register(i);
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end if;
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end loop;
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end if;
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end process;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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