| Line 131... |
Line 131... |
allow_rwcycle_when_full => "OFF",
|
allow_rwcycle_when_full => "OFF",
|
intended_device_family => "Cyclone III",
|
intended_device_family => "Cyclone III",
|
lpm_hint => "RAM_BLOCK_TYPE=M9K",
|
lpm_hint => "RAM_BLOCK_TYPE=M9K",
|
almost_full_value => 32,
|
almost_full_value => 32,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "OFF",
|
lpm_type => "SCFIFO",
|
lpm_type => "SCFIFO",
|
lpm_width => 96,
|
lpm_width => 96,
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
| Line 180... |
Line 180... |
data => s0ext_d,
|
data => s0ext_d,
|
almost_full => open
|
almost_full => open
|
);
|
);
|
|
|
--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracció:n de código, no influye en la sintesis del circuito.
|
--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracció:n de código, no influye en la sintesis del circuito.
|
sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
|
sint_rd_add (0)<= int_rd_add(widthadmemblock-1-memoryreduction downto 0);
|
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
|
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1-memoryreduction downto widthadmemblock);
|
|
|
--! Instanciación de la cola de resultados de salida.
|
--! Instanciación de la cola de resultados de salida.
|
int_q <= s1int_q;
|
int_q <= s1int_q;
|
operands_blocks:
|
operands_blocks:
|
for i in 11 downto 0 generate
|
for i in 11 downto 0 generate
|
| Line 197... |
Line 197... |
clock_enable_input_a => "BYPASS",
|
clock_enable_input_a => "BYPASS",
|
clock_enable_input_b => "BYPASS",
|
clock_enable_input_b => "BYPASS",
|
clock_enable_output_b => "BYPASS",
|
clock_enable_output_b => "BYPASS",
|
intended_device_family => "Cyclone III",
|
intended_device_family => "Cyclone III",
|
lpm_type => "altsyncram",
|
lpm_type => "altsyncram",
|
numwords_a => 2**widthadmemblock,
|
numwords_a => 2**(widthadmemblock-memoryreduction),
|
numwords_b => 2**widthadmemblock,
|
numwords_b => 2**(widthadmemblock-memoryreduction),
|
operation_mode => "DUAL_PORT",
|
operation_mode => "DUAL_PORT",
|
outdata_aclr_b => "NONE",
|
outdata_aclr_b => "NONE",
|
outdata_reg_b => "CLOCK0",
|
outdata_reg_b => "CLOCK0",
|
power_up_uninitialized => "FALSE",
|
power_up_uninitialized => "FALSE",
|
ram_block_type => "M9K",
|
ram_block_type => "M9K",
|
rdcontrol_reg_b => "CLOCK0",
|
rdcontrol_reg_b => "CLOCK0",
|
read_during_write_mode_mixed_ports => "OLD_DATA",
|
read_during_write_mode_mixed_ports => "OLD_DATA",
|
widthad_a => widthadmemblock,
|
widthad_a => widthadmemblock-memoryreduction,
|
widthad_b => widthadmemblock,
|
widthad_b => widthadmemblock-memoryreduction,
|
width_a => floatwidth,
|
width_a => floatwidth,
|
width_b => floatwidth,
|
width_b => floatwidth,
|
width_byteena_a => 1
|
width_byteena_a => 1
|
)
|
)
|
port map (
|
port map (
|
wren_a => s0ext_wr_add_one_hot(i),
|
wren_a => s0ext_wr_add_one_hot(i),
|
clock0 => clk,
|
clock0 => clk,
|
address_a => s0ext_wr_add(widthadmemblock-1 downto 0),
|
address_a => s0ext_wr_add(widthadmemblock-1-memoryreduction downto 0),
|
address_b => sint_rd_add((i/3) mod 2),
|
address_b => sint_rd_add((i/3) mod 2),
|
rden_b => '1',
|
rden_b => '1',
|
q_b => s1int_q(i),
|
q_b => s1int_q(i),
|
data_a => s0ext_d
|
data_a => s0ext_d
|
);
|
);
|
| Line 234... |
Line 234... |
results_blocks:
|
results_blocks:
|
for i in 7 downto 0 generate
|
for i in 7 downto 0 generate
|
resultsfifo : scfifo
|
resultsfifo : scfifo
|
generic map (
|
generic map (
|
add_ram_output_register => "OFF",
|
add_ram_output_register => "OFF",
|
almost_full_value => 480,
|
almost_full_value => 224,
|
allow_rwcycle_when_full => "OFF",
|
allow_rwcycle_when_full => "OFF",
|
intended_device_family => "Cyclone III",
|
intended_device_family => "Cyclone III",
|
lpm_hint => "RAM_BLOCK_TYPE=M9K",
|
lpm_hint => "RAM_BLOCK_TYPE=M9K",
|
lpm_numwords => 512,
|
lpm_numwords => 256,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_type => "SCIFIFO",
|
lpm_type => "SCIFIFO",
|
lpm_width => 32,
|
lpm_width => 32,
|
lpm_widthu => 9,
|
lpm_widthu => 8,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
