Subversion Repositories raytrac

                --! Interrupciones

                --! Interrupciones

                int     : out std_logic_vector (7 downto 0);

                int     : out std_logic_vector (7 downto 0);

                --! Salidas

                --! Salidas

        );

        );

end entity;

end entity;

architecture raytrac_arch of raytrac is

architecture raytrac_arch of raytrac is

        --! Instanciar el bloque de memorias MEMBLOCK

        --! Instanciar el bloque de memorias MEMBLOCK

        MemoryBlock : memblock

        MemoryBlock : memblock

        generic map (

        generic map (

                blocksize                                       => 512,

                blocksize                                       => 512,

                external_writeable_blocks       => 12,

                external_writeable_blocks       => 12,

                external_readable_blocks        => 8,

                external_readable_blocks        => 8,

                external_readable_widthad       => 3,

                external_readable_widthad       => 3,

                external_writeable_widthad      => 4

                external_writeable_widthad      => 4

        )

        )

                dpfifo_d                        => s_dpfifo_d,

                dpfifo_d                        => s_dpfifo_d,

                normfifo_d                      => s_normfifo_d,

                normfifo_d                      => s_normfifo_d,

                dpfifo_q                        => s_dpfifo_q,

                dpfifo_q                        => s_dpfifo_q,

                normfifo_q                      => s_normfifo_q

                normfifo_q                      => s_normfifo_q

        );

        );

        --! Instanciar el bloque DPC

        --! Instanciar el bloque DPC

        DataPathControl_And_Syncronization_Block: dpc

        DataPathControl_And_Syncronization_Block: dpc

        port map (

        port map (

                clk                             => clk,

                clk                             => clk,

                rst                             => rst,

                rst                             => rst,

                paraminput              => s_q,

                paraminput              => s_q,

                fifo32x23_r             => s_normfifo_r,

                fifo32x23_r             => s_normfifo_r,

                resf_vector             => s_rfull_events,

                resf_vector             => s_rfull_events,

                resf_event              => s_full_r,

                resf_event              => s_full_r,

                resultoutput    => s_results_d

                resultoutput    => s_results_d

        );

        );

        --! Instanciar el bloque de inversion

        --! Instanciar el bloque de inversion

        inversion_block : invr32

        inversion_block : invr32

        port map (

        port map (

                clk             => clk,

                clk             => clk,

                dvd32   => s_dvd32,

                dvd32   => s_dvd32,

                qout32  => s_qout32

                qout32  => s_qout32

        );

        );

        --! Instanciar el bloque de raíz cuadrada.

        --! Instanciar el bloque de raíz cuadrada.

        square_root : sqrt32

        square_root : sqrt32

        port map (

        port map (

                clk     => clk,

                clk     => clk,

                rd32    => s_rd32,

                rd32    => s_rd32,

                sq32    => s_sq32

                sq32    => s_sq32

        );

        );

        --! Instanciar el bloque aritmético.

        --! Instanciar el bloque aritmético.

        arithmetic_block : arithblock

        arithmetic_block : arithblock

        port map (

        port map (

                clk => clk,

                clk => clk,

                rst => rst,

                rst => rst,

                dpc => s_dpc_uca(1),

                dpc => s_dpc_uca(1),

                f       => s_f,

                f       => s_f,

                a       => s_a,

                a       => s_a,

                s       => s_s,

                s       => s_s,

                p       => s_p

                p       => s_p

        );

        );

        --! Instanciar la maquina de interrupciones

        --! Instanciar la maquina de interrupciones

        interruption_machine : im

        interruption_machine : im

        generic map (

        generic map (

                num_events              => 4,

                num_events              => 4,

                cycles_to_wait  => 1023

                cycles_to_wait  => 1023

        )

        )

                eoi_int                 => int(3 downto 0),

                eoi_int                 => int(3 downto 0),

                rfull_int               => int(7 downto 4),

                rfull_int               => int(7 downto 4),

                state                   => s_iCtrlState

                state                   => s_iCtrlState

        );

        );

        --!Instanciar la maquina de estados

        --!Instanciar la maquina de estados

        state_machine : sm

        state_machine : sm

        port map (

        port map (

                clk                     => clk,

                clk                     => clk,

                rst                     => rst,

                rst                     => rst,

                instrQq                 => s_iq,

                instrQq                 => s_iq,

                instrQ_empty    => s_iq_empty,

                instrQ_empty    => s_iq_empty,

                eoi                             => s_eoi,

                eoi                             => s_eoi,

                dpc_uca                 => s_dpc_uca,

                dpc_uca                 => s_dpc_uca,

                state                   => s_smState

                state                   => s_smState

        );

        );

end architecture;

end architecture;

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