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[/] [raytrac/] [branches/] [fp/] [raytrac.vhd] - Diff between revs 152 and 157

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Rev 152 Rev 157
Line 57... Line 57...
 
 
architecture raytrac_arch of raytrac is
architecture raytrac_arch of raytrac is
 
 
        --! Señales de State Machine -> Memblock
        --! Señales de State Machine -> Memblock
        --!TBXSTART:SM
        --!TBXSTART:SM
 
        signal s_int_rd_add             : std_logic_vector (17 downto 0);
        signal s_adda                   : std_logic_vector (8 downto 0);
        signal s_adda                   : std_logic_vector (8 downto 0);
        signal s_addb                   : std_logic_vector (8 downto 0);
        signal s_addb                   : std_logic_vector (8 downto 0);
        signal s_iq_rd_ack              : std_logic;
        signal s_iq_rd_ack              : std_logic;
        --! Señales de State Machine -> DataPathControl
        --! Señales de State Machine -> DataPathControl
        signal s_sync_chain_0   : std_logic;
        signal s_sync_chain_0   : std_logic;
Line 95... Line 96...
        signal s_rd32                   : std_logic_vector (31 downto 0);
        signal s_rd32                   : std_logic_vector (31 downto 0);
        --! Señales de DPC a inv32.
        --! Señales de DPC a inv32.
        signal s_dvd32                  : std_logic_vector (31 downto 0);
        signal s_dvd32                  : std_logic_vector (31 downto 0);
        --! Señales de DPC  a invr32.
        --! Señales de DPC  a invr32.
        --! Se&ntilde que va desde DPC -> Memblock
        --! Se&ntilde que va desde DPC -> Memblock
 
        signal s_resultfifo_wr  : std_logic_vector (7 downto 0);
        signal s_resultsfifo_w  : std_logic_vector (4 downto 0);
        signal s_resultsfifo_w  : std_logic_vector (4 downto 0);
        signal s_dpfifo_w               : std_logic;
        signal s_dpfifo_w               : std_logic;
        signal s_dpfifo_r               : std_logic;
        signal s_dpfifo_r               : std_logic;
        signal s_dpfifo_d               : std_logic_vector (2*32-1 downto 0);
        signal s_dpfifo_d               : std_logic_vector (2*32-1 downto 0);
        signal s_normfifo_w             : std_logic;
        signal s_normfifo_w             : std_logic;
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        --! Instanciar el bloque de memorias MEMBLOCK
        --! Instanciar el bloque de memorias MEMBLOCK
 
        s_resultfifo_wr <= s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0);
 
        s_int_rd_add  <= s_addb&s_adda;
        --!TBXINSTANCESTART
        --!TBXINSTANCESTART
        MemoryBlock : memblock
        MemoryBlock : memblock
        generic map (
        generic map (
                blocksize                                       => 512,
                blocksize                                       => 512,
                external_writeable_blocks       => 12,
                external_writeable_blocks       => 12,
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                dpfifo_rd                       => s_dpfifo_r,
                dpfifo_rd                       => s_dpfifo_r,
                normfifo_rd                     => s_normfifo_r,
                normfifo_rd                     => s_normfifo_r,
                dpfifo_wr                       => s_dpfifo_w,
                dpfifo_wr                       => s_dpfifo_w,
                normfifo_wr                     => s_normfifo_w,
                normfifo_wr                     => s_normfifo_w,
                instrfifo_rd            => s_iq_rd_ack,
                instrfifo_rd            => s_iq_rd_ack,
                resultfifo_wr           => s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0),
                resultfifo_wr           => s_resultfifo_wr,
                instrfifo_empty         => s_iq_empty,
                instrfifo_empty         => s_iq_empty,
                ext_rd                          => rd,
                ext_rd                          => rd,
                ext_wr                          => wr,
                ext_wr                          => wr,
                ext_wr_add                      => add,
                ext_wr_add                      => add,
                ext_rd_add                      => add(12 downto 10),
                ext_rd_add                      => add(12 downto 10),
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                resultfifo_full         => s_rfull_events,
                resultfifo_full         => s_rfull_events,
                int_d                           => s_results_d,
                int_d                           => s_results_d,
                ext_q                           => q,
                ext_q                           => q,
                instrfifo_q                     => s_iq,
                instrfifo_q                     => s_iq,
                int_q                           => s_q,
                int_q                           => s_q,
                int_rd_add                      => s_addb&s_adda,
                int_rd_add                      => s_int_rd_add,
                dpfifo_d                        => s_dpfifo_d,
                dpfifo_d                        => s_dpfifo_d,
                normfifo_d                      => s_normfifo_d,
                normfifo_d                      => s_normfifo_d,
                dpfifo_q                        => s_dpfifo_q,
                dpfifo_q                        => s_dpfifo_q,
                normfifo_q                      => s_normfifo_q
                normfifo_q                      => s_normfifo_q
        );
        );

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