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architecture raytrac_arch of raytrac is
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architecture raytrac_arch of raytrac is
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--! Señales de State Machine -> Memblock
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--! Señales de State Machine -> Memblock
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--!TBXSTART:SM
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--!TBXSTART:SM
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signal s_int_rd_add : std_logic_vector (17 downto 0);
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signal s_adda : std_logic_vector (8 downto 0);
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signal s_adda : std_logic_vector (8 downto 0);
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signal s_addb : std_logic_vector (8 downto 0);
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signal s_addb : std_logic_vector (8 downto 0);
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signal s_iq_rd_ack : std_logic;
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signal s_iq_rd_ack : std_logic;
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--! Señales de State Machine -> DataPathControl
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--! Señales de State Machine -> DataPathControl
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signal s_sync_chain_0 : std_logic;
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signal s_sync_chain_0 : std_logic;
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signal s_rd32 : std_logic_vector (31 downto 0);
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signal s_rd32 : std_logic_vector (31 downto 0);
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--! Señales de DPC a inv32.
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--! Señales de DPC a inv32.
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signal s_dvd32 : std_logic_vector (31 downto 0);
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signal s_dvd32 : std_logic_vector (31 downto 0);
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--! Señales de DPC a invr32.
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--! Señales de DPC a invr32.
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--! Señ que va desde DPC -> Memblock
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--! Señ que va desde DPC -> Memblock
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signal s_resultfifo_wr : std_logic_vector (7 downto 0);
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signal s_resultsfifo_w : std_logic_vector (4 downto 0);
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signal s_resultsfifo_w : std_logic_vector (4 downto 0);
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signal s_dpfifo_w : std_logic;
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signal s_dpfifo_w : std_logic;
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signal s_dpfifo_r : std_logic;
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signal s_dpfifo_r : std_logic;
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signal s_dpfifo_d : std_logic_vector (2*32-1 downto 0);
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signal s_dpfifo_d : std_logic_vector (2*32-1 downto 0);
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signal s_normfifo_w : std_logic;
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signal s_normfifo_w : std_logic;
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--! Instanciar el bloque de memorias MEMBLOCK
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--! Instanciar el bloque de memorias MEMBLOCK
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s_resultfifo_wr <= s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0);
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s_int_rd_add <= s_addb&s_adda;
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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MemoryBlock : memblock
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MemoryBlock : memblock
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generic map (
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generic map (
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blocksize => 512,
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blocksize => 512,
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external_writeable_blocks => 12,
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external_writeable_blocks => 12,
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dpfifo_rd => s_dpfifo_r,
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dpfifo_rd => s_dpfifo_r,
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normfifo_rd => s_normfifo_r,
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normfifo_rd => s_normfifo_r,
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dpfifo_wr => s_dpfifo_w,
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dpfifo_wr => s_dpfifo_w,
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normfifo_wr => s_normfifo_w,
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normfifo_wr => s_normfifo_w,
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instrfifo_rd => s_iq_rd_ack,
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instrfifo_rd => s_iq_rd_ack,
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resultfifo_wr => s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0),
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resultfifo_wr => s_resultfifo_wr,
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instrfifo_empty => s_iq_empty,
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instrfifo_empty => s_iq_empty,
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ext_rd => rd,
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ext_rd => rd,
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ext_wr => wr,
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ext_wr => wr,
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ext_wr_add => add,
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ext_wr_add => add,
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ext_rd_add => add(12 downto 10),
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ext_rd_add => add(12 downto 10),
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resultfifo_full => s_rfull_events,
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resultfifo_full => s_rfull_events,
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int_d => s_results_d,
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int_d => s_results_d,
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ext_q => q,
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ext_q => q,
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instrfifo_q => s_iq,
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instrfifo_q => s_iq,
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int_q => s_q,
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int_q => s_q,
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int_rd_add => s_addb&s_adda,
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int_rd_add => s_int_rd_add,
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dpfifo_d => s_dpfifo_d,
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dpfifo_d => s_dpfifo_d,
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normfifo_d => s_normfifo_d,
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normfifo_d => s_normfifo_d,
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dpfifo_q => s_dpfifo_q,
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dpfifo_q => s_dpfifo_q,
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normfifo_q => s_normfifo_q
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normfifo_q => s_normfifo_q
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);
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);
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