| Line 43... |
Line 43... |
|
|
--! datos de entrada
|
--! datos de entrada
|
d : in std_logic_vector (31 downto 0);
|
d : in std_logic_vector (31 downto 0);
|
|
|
--! Interrupciones
|
--! Interrupciones
|
int07,int06,int05,int04,int03,int02,int01,int00 : out std_logic;
|
int : out std_logic;
|
|
|
--! Salidas
|
--! Salidas
|
q : out std_logic_vector (31 downto 0)
|
q : out std_logic_vector (31 downto 0)
|
|
|
|
|
| Line 125... |
Line 125... |
signal s_resultsfifo_w : std_logic_vector (4 downto 0);
|
signal s_resultsfifo_w : std_logic_vector (4 downto 0);
|
|
|
--!TBXSTART:IM
|
--!TBXSTART:IM
|
--! Señales de Interruption Machine al testbench
|
--! Señales de Interruption Machine al testbench
|
signal s_iCtrlState : iCtrlState;
|
signal s_iCtrlState : iCtrlState;
|
signal s_int : std_logic_vector (7 downto 0);
|
signal s_int : std_logic;
|
--!TBXEND
|
--!TBXEND
|
begin
|
begin
|
|
|
--! Sacar las interrupciones
|
--! Sacar las interrupciones
|
int07 <= s_int(7);
|
int <= s_int;
|
int06 <= s_int(6);
|
|
int05 <= s_int(5);
|
|
int04 <= s_int(4);
|
|
int03 <= s_int(3);
|
|
int02 <= s_int(2);
|
|
int01 <= s_int(1);
|
|
int00 <= s_int(0);
|
|
|
|
--! Signo de los bloques de suma
|
--! Signo de los bloques de suma
|
s_sign <= not(s_dpc_uca(2)) and s_dpc_uca(1);
|
s_sign <= not(s_dpc_uca(2)) and s_dpc_uca(1);
|
--! Instanciar el bloque de memorias MEMBLOCK
|
--! Instanciar el bloque de memorias MEMBLOCK
|
s_resultfifo_wr <= s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0);
|
s_resultfifo_wr <= s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0);
|
s_int_rd_add <= s_addb&s_adda;
|
s_int_rd_add <= s_addb&s_adda;
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
MemoryBlock : memblock
|
MemoryBlock : memblock
|
generic map (
|
|
blocksize => 512,
|
|
external_readable_widthad => 3,
|
|
external_writeable_widthad => 4
|
|
)
|
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
dpfifo_rd => s_dpfifo_r,
|
dpfifo_rd => s_dpfifo_r,
|
normfifo_rd => s_normfifo_r,
|
normfifo_rd => s_normfifo_r,
|
| Line 164... |
Line 152... |
resultfifo_wr => s_resultfifo_wr,
|
resultfifo_wr => s_resultfifo_wr,
|
instrfifo_empty => s_iq_empty,
|
instrfifo_empty => s_iq_empty,
|
ext_rd => rd,
|
ext_rd => rd,
|
ext_wr => wr,
|
ext_wr => wr,
|
ext_wr_add => add,
|
ext_wr_add => add,
|
ext_rd_add => add(12 downto 10),
|
ext_rd_add => add(12 downto 9),
|
ext_d => d,
|
ext_d => d,
|
resultfifo_full => s_rfull_events,
|
resultfifo_full => s_rfull_events,
|
int_d => s_results_d,
|
int_d => s_results_d,
|
|
status_register => s_eoi_events,
|
ext_q => q,
|
ext_q => q,
|
instrfifo_q => s_iq,
|
instrfifo_q => s_iq,
|
int_q => s_q,
|
int_q => s_q,
|
int_rd_add => s_int_rd_add,
|
int_rd_add => s_int_rd_add,
|
dpfifo_d => s_dpfifo_d,
|
dpfifo_d => s_dpfifo_d,
|
| Line 261... |
Line 250... |
cycles_to_wait => 1023
|
cycles_to_wait => 1023
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
rfull_events => s_rfull_events,
|
rfull_event => s_full_r,
|
eoi_events => s_eoi_events,
|
eoi_event => s_eoi,
|
eoi_int => s_int(3 downto 0),
|
int => s_int,
|
rfull_int => s_int(7 downto 4),
|
|
state => s_iCtrlState
|
state => s_iCtrlState
|
|
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
--!Instanciar la maquina de estados
|
--!Instanciar la maquina de estados
|
