| Line 21... |
Line 21... |
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
|
|
|
entity sm is
|
entity sm is
|
generic (
|
|
width :integer:= 32;
|
|
widthadmemblock : integer := 9
|
|
);
|
|
port (
|
port (
|
|
|
clk,rst: in std_logic;
|
clk,rst: in std_logic;
|
add_rd,add_wr:out std_logic_vector(widthadmemblock-1 downto 0);
|
add0,add1:out std_logic_vector (8 downto 0);
|
iempty,ifull:in std_logic_vector;
|
iq:in std_logic_vector(31 downto 0);
|
rd,wr:out std_logic;
|
read_memory,ird_ack:out std_logic;
|
irq:out std_logic
|
ucsa:out std_logic(3 downto 0);
|
|
iempty , rfull, opq_empty : in std_logic;
|
);
|
);
|
end entity;
|
end entity;
|
architecture sm_arch of arch is
|
|
|
architecture sm_arch of sm is
|
|
|
|
type macState is (IDLE,EXECUTING,FLUSHING);
|
|
signal state : macState;
|
|
constant rstMasterValue : std_logic:='0';
|
|
|
|
|
|
|
|
|
|
signal sadd0,sadd1:std_logic_vector (8 downto 0);
|
|
signal schunk0o,schunk0f,schunk1o,schunk1f: std_logic_vector (3 downto 0);
|
|
signal sadd0_now,sadd0_next,sadd0_reg:std_logic_vector(8 downto 0);
|
|
signal sadd1_now,sadd1_next,sadd1_reg:std_logic_vector(8 downto 0);
|
|
signal sadd0_adder_bit,sadd1_adder_bit,sena:std_logic;
|
|
|
|
|
begin
|
begin
|
|
|
|
|
|
schunk0o(3 downto 0) <= iq(19 downto 16);
|
|
schunk0f(3 downto 0) <= iq(15 downto 12);
|
|
schunk1o(3 downto 0) <= iq(11 downto 8);
|
|
schunk1f(3 downto 0) <= iq(7 downto 4);
|
|
|
|
ucsa <= iq(3 downto 0);
|
|
|
|
sadd0_next <= sadd0_now+sadd0_adder_bit;
|
|
sadd1_next <= sadd1_now+sadd1_adder_bit;
|
|
|
|
|
|
sm_comb:
|
|
process (state)
|
|
begin
|
|
case state is
|
|
when IDLE =>
|
|
sadd0_now <= schunk0o(3 downto 0)&x"0";
|
|
sadd1_now <= schunk1o(3 downto 0)&x"0";
|
|
when others =>
|
|
sadd0_now <= sadd0_next;
|
|
sadd1_now <= sadd1_next;
|
|
end case;
|
|
|
|
end process;
|
|
|
|
|
|
sm_proc:
|
|
process (clk,rst)
|
|
begin
|
|
if rst=rstMasterValue then
|
|
state <= IDLE;
|
|
ird_ack <= '0';
|
|
elsif clk='1' and clk'event and sena='1' then
|
|
|
|
case state is
|
|
when IDLE =>
|
|
if rfull='0' and iempty='0' then
|
|
state <= EXECUTING;
|
|
read_memory <= '1';
|
|
end if;
|
|
when EXCUTING =>
|
|
if rfull='0' then
|
|
if sadd1_now=schunk1f&"11111" then
|
|
if sadd0_now=schunk0f&"11111" then
|
|
state <= FLUSHING;
|
|
|
|
end if;
|
|
end if;
|
|
end if;
|
|
when FLUSHING =>
|
|
if opq_empty='1' then
|
|
|
|
end if;
|
|
end case;
|
|
end if;
|
|
|
|
end process;
|
|
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
