OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [ap_n_dpc.vhd] - Diff between revs 229 and 230

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 229 Rev 230
Line 30... Line 30... 
 
 
 
 
 
 
 
 
entity ap_n_dpc is
 
entity ap_n_dpc is
 
 
 
 
 
        port (
 
        port (
 
                sumando5                                : out   std_logic_vector(31 downto 0);
 
 
 
 
 
 
 
                clk                                             : in    std_logic;
 
                clk                                             : in    std_logic;
 
                rst                                             : in    std_logic;
 
                rst                                             : in    std_logic;
 
 
 
 
 
                dx                                              : out   std_logic_vector(31 downto 0);
 
 
 
                dy                                              : out   std_logic_vector(31 downto 0);
 
 
 
                dz                                              : out   std_logic_vector(31 downto 0);
 
 
 
                dsc                                             : out   std_logic_vector(31 downto 0);
 
 
 
                ax                                              : in    std_logic_vector(31 downto 0);
 
                ax                                              : in    std_logic_vector(31 downto 0);
 
                ay                                              : in    std_logic_vector(31 downto 0);
 
                ay                                              : in    std_logic_vector(31 downto 0);
 
                az                                              : in    std_logic_vector(31 downto 0);
 
                az                                              : in    std_logic_vector(31 downto 0);
 
                bx                                              : in    std_logic_vector(31 downto 0);
 
                bx                                              : in    std_logic_vector(31 downto 0);
 
                by                                              : in    std_logic_vector(31 downto 0);
 
                by                                              : in    std_logic_vector(31 downto 0);
Line 115... Line 110... 
        --signal sprd32blk      : vectorblock06;
 
        --signal sprd32blk      : vectorblock06;
 
 
 
 
 
        signal sa0                      : std_logic_vector(31 downto 0);
 
        signal sa0                      : std_logic_vector(31 downto 0);
 
        signal sa1                      : std_logic_vector(31 downto 0);
 
        signal sa1                      : std_logic_vector(31 downto 0);
 
        signal sa2                      : std_logic_vector(31 downto 0);
 
        signal sa2                      : std_logic_vector(31 downto 0);
 
        signal sa3                      : std_logic_vector(31 downto 0);
 
        constant adder2_delay: integer := 2;
 
 
 
 
 
        --signal sadd32blk      : vectorblock03;
 
        --signal sadd32blk      : vectorblock03;
 
 
 
 
 
        signal ssq32    : std_logic_vector(31 downto 0);
 
        signal ssq32    : std_logic_vector(31 downto 0);
 
        signal sinv32   : std_logic_vector(31 downto 0);
 
        signal sinv32   : std_logic_vector(31 downto 0);
Line 156... Line 151... 
 
 
 
 
 
 
 
 
        signal sa0o                     : std_logic_vector(31 downto 0);
 
        signal sa0o                     : std_logic_vector(31 downto 0);
 
        signal sa1o                     : std_logic_vector(31 downto 0);
 
        signal sa1o                     : std_logic_vector(31 downto 0);
 
        signal sa2o                     : std_logic_vector(31 downto 0);
 
        signal sa2o                     : std_logic_vector(31 downto 0);
 
        signal sa3o                     : std_logic_vector(31 downto 0);
 
 
 
        --signal sadd32blko     : vectorblock03;        --! Salidas de los 3 sumadores.
 
        --signal sadd32blko     : vectorblock03;        --! Salidas de los 3 sumadores.
 
 
 
 
 
        signal sp0o                     : std_logic_vector(31 downto 0);
 
        signal sp0o                     : std_logic_vector(31 downto 0);
 
        signal sp1o                     : std_logic_vector(31 downto 0);
 
        signal sp1o                     : std_logic_vector(31 downto 0);
 
        signal sp2o                     : std_logic_vector(31 downto 0);
 
        signal sp2o                     : std_logic_vector(31 downto 0);
Line 204... Line 198... 
                --add32blki     : in vectorblock06;
 
                --add32blki     : in vectorblock06;
 
 
 
 
 
                a0                      : out std_logic_vector(31 downto 0);
 
                a0                      : out std_logic_vector(31 downto 0);
 
                a1                      : out std_logic_vector(31 downto 0);
 
                a1                      : out std_logic_vector(31 downto 0);
 
                a2                      : out std_logic_vector(31 downto 0);
 
                a2                      : out std_logic_vector(31 downto 0);
 
                a3                      : out std_logic_vector(31 downto 0);
 
 
 
                --add32blko     : out vectorblock03;
 
                --add32blko     : out vectorblock03;
 
 
 
 
 
                p0                      : out std_logic_vector(31 downto 0);
 
                p0                      : out std_logic_vector(31 downto 0);
 
                p1                      : out std_logic_vector(31 downto 0);
 
                p1                      : out std_logic_vector(31 downto 0);
 
                p2                      : out std_logic_vector(31 downto 0);
 
                p2                      : out std_logic_vector(31 downto 0);
Line 222... Line 215... 
 
 
 
 
        );
 
        );
 
        end component;
 
        end component;
 
 
 
 
 
begin
 
begin
 
        --! Debug
 
 
 
        sumando5 <= sa2o;
 
 
 
 
 
 
 
        --! Bloque Aritm&eacute;tico
 
        --! Bloque Aritm&eacute;tico
 
        ap : arithblock
 
        ap : arithblock
 
        port map (
 
        port map (
 
                clk             => clk,
 
                clk             => clk,
Line 258... Line 249... 
                --add32blki     => ssumando,
 
                --add32blki     => ssumando,
 
 
 
 
 
                a0=>sa0o,
 
                a0=>sa0o,
 
                a1=>sa1o,
 
                a1=>sa1o,
 
                a2=>sa2o,
 
                a2=>sa2o,
 
                a3=>sa3o,
 
 
 
                --add32blko     => sadd32blko, 
                --add32blko     => sadd32blko, 
 
 
 
 
                p0=>sp0o,
 
                p0=>sp0o,
 
                p1=>sp1o,
 
                p1=>sp1o,
 
                p2=>sp2o,
 
                p2=>sp2o,
Line 281... Line 271... 
        sync_chain_proc:
 
        sync_chain_proc:
 
        process(clk,rst,sync_chain_1)
 
        process(clk,rst,sync_chain_1)
 
        begin
 
        begin
 
                if rst=rstMasterValue then
 
                if rst=rstMasterValue then
 
                        ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
 
                        ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
 
                        dx <= (others => '0');
 
 
 
                        dy <= (others => '0');
 
 
 
                        dz <= (others => '0');
 
 
 
                        dsc <= (others => '0');
 
 
 
                elsif clk'event and clk='1' then
 
 
 
 
 
 
 
                        if sqr_w='1' then
 
 
 
                                dx <= ssumando4;
 
 
 
                                dy <= ssumando5;
 
 
 
                                dz <= sa3;
 
 
 
                                dsc <= sqr_dsc;
 
 
 
                        end if;
 
 
 
 
 
 
 
 
 
 
 
 
 
                elsif clk'event and clk='1' then
 
                        for i in ssync_chain_max downto ssync_chain_min+1 loop
 
                        for i in ssync_chain_max downto ssync_chain_min+1 loop
 
                                ssync_chain(i) <= ssync_chain(i-1);
 
                                ssync_chain(i) <= ssync_chain(i-1);
 
                        end loop;
 
                        end loop;
 
                        ssync_chain(ssync_chain_min) <= sync_chain_1;
 
                        ssync_chain(ssync_chain_min) <= sync_chain_1;
 
                end if;
 
                end if;
Line 320... Line 298... 
                        sp4 <= sp4o;
 
                        sp4 <= sp4o;
 
                        sp5 <= sp5o;
 
                        sp5 <= sp5o;
 
                        sa0 <= sa0o;
 
                        sa0 <= sa0o;
 
                        sa1 <= sa1o;
 
                        sa1 <= sa1o;
 
                        sa2 <= sa2o;
 
                        sa2 <= sa2o;
 
                        sa3 <= sa3o;
 
 
 
                        sinv32 <= sinv32o;
 
                        sinv32 <= sinv32o;
 
                        ssq32 <= ssq32o;
 
                        ssq32 <= ssq32o;
 
                end if;
 
                end if;
 
        end process;
 
        end process;
 
 
 
 
Line 360... Line 337... 
 
 
 
 
                                sqr_dx <= sa0;
 
                                sqr_dx <= sa0;
 
                                sqr_dy <= sa1;
 
                                sqr_dy <= sa1;
 
                                sqr_dz <= sa2;
 
                                sqr_dz <= sa2;
 
 
 
 
 
                                sqr_w <= ssync_chain(13);
 
                                sqr_w <= ssync_chain(13+adder2_delay);
 
 
 
 
 
                        when"000"|"001" =>
 
                        when"000"|"001" =>
 
 
 
 
 
                                sq2_w <= '0';
 
                                sq2_w <= '0';
 
                                sq2_d <= ssq32;
 
                                sq2_d <= ssq32;
Line 392... Line 369... 
 
 
 
 
                                sqr_dx <= sa0;
 
                                sqr_dx <= sa0;
 
                                sqr_dy <= sa1;
 
                                sqr_dy <= sa1;
 
                                sqr_dz <= sa2;
 
                                sqr_dz <= sa2;
 
 
 
 
 
                                sqr_w <= ssync_chain(9);
 
                                sqr_w <= ssync_chain(9+adder2_delay);
 
 
 
 
 
                        when"110" |"100" =>
 
                        when"110" |"100" =>
 
 
 
 
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.