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architecture ap_n_dpc_arch of ap_n_dpc is
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architecture ap_n_dpc_arch of ap_n_dpc is
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--!Constantes de apoyo
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--!Constantes de apoyo
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constant ssync_chain_max : integer :=27;
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constant ssync_chain_max : integer :=27;
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constant ssync_chain_min : integer :=2;
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constant ssync_chain_min : integer :=2;
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--! Tunnning delay
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constant adder2_delay: integer := 1;
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--!TBXSTART:FACTORS_N_ADDENDS
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--!TBXSTART:FACTORS_N_ADDENDS
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signal sfactor0 : std_logic_vector(31 downto 0);
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signal sfactor0 : std_logic_vector(31 downto 0);
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signal sfactor1 : std_logic_vector(31 downto 0);
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signal sfactor1 : std_logic_vector(31 downto 0);
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--signal sprd32blk : vectorblock06;
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--signal sprd32blk : vectorblock06;
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signal sa0 : std_logic_vector(31 downto 0);
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signal sa0 : std_logic_vector(31 downto 0);
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signal sa1 : std_logic_vector(31 downto 0);
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signal sa1 : std_logic_vector(31 downto 0);
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signal sa2 : std_logic_vector(31 downto 0);
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signal sa2 : std_logic_vector(31 downto 0);
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constant adder2_delay: integer := 2;
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--signal sadd32blk : vectorblock03;
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--signal sadd32blk : vectorblock03;
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signal ssq32 : std_logic_vector(31 downto 0);
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signal ssq32 : std_logic_vector(31 downto 0);
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signal sinv32 : std_logic_vector(31 downto 0);
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signal sinv32 : std_logic_vector(31 downto 0);
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)
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)
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port map (
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port map (
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sclr => '0',
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sclr => '0',
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clock => clk,
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clock => clk,
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rdreq => ssync_chain(13),
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rdreq => ssync_chain(13),
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wrreq => ssync_chain(5),
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wrreq => ssync_chain(5+adder2_delay),
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data => sp2,
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data => sp2,
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q => sq0_q
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q => sq0_q
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);
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);
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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q2 : scfifo --! Debe ir registrada la salida.
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q2 : scfifo --! Debe ir registrada la salida.
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