| Line 68... |
Line 68... |
architecture ap_n_dpc_arch of ap_n_dpc is
|
architecture ap_n_dpc_arch of ap_n_dpc is
|
--!Constantes de apoyo
|
--!Constantes de apoyo
|
constant ssync_chain_max : integer :=27;
|
constant ssync_chain_max : integer :=27;
|
constant ssync_chain_min : integer :=2;
|
constant ssync_chain_min : integer :=2;
|
|
|
|
--! Tunnning delay
|
|
constant adder2_delay: integer := 1;
|
|
|
|
|
--!TBXSTART:FACTORS_N_ADDENDS
|
--!TBXSTART:FACTORS_N_ADDENDS
|
signal sfactor0 : std_logic_vector(31 downto 0);
|
signal sfactor0 : std_logic_vector(31 downto 0);
|
signal sfactor1 : std_logic_vector(31 downto 0);
|
signal sfactor1 : std_logic_vector(31 downto 0);
|
| Line 110... |
Line 112... |
--signal sprd32blk : vectorblock06;
|
--signal sprd32blk : vectorblock06;
|
|
|
signal sa0 : std_logic_vector(31 downto 0);
|
signal sa0 : std_logic_vector(31 downto 0);
|
signal sa1 : std_logic_vector(31 downto 0);
|
signal sa1 : std_logic_vector(31 downto 0);
|
signal sa2 : std_logic_vector(31 downto 0);
|
signal sa2 : std_logic_vector(31 downto 0);
|
constant adder2_delay: integer := 2;
|
|
|
|
--signal sadd32blk : vectorblock03;
|
--signal sadd32blk : vectorblock03;
|
|
|
signal ssq32 : std_logic_vector(31 downto 0);
|
signal ssq32 : std_logic_vector(31 downto 0);
|
signal sinv32 : std_logic_vector(31 downto 0);
|
signal sinv32 : std_logic_vector(31 downto 0);
|
| Line 466... |
Line 467... |
)
|
)
|
port map (
|
port map (
|
sclr => '0',
|
sclr => '0',
|
clock => clk,
|
clock => clk,
|
rdreq => ssync_chain(13),
|
rdreq => ssync_chain(13),
|
wrreq => ssync_chain(5),
|
wrreq => ssync_chain(5+adder2_delay),
|
data => sp2,
|
data => sp2,
|
q => sq0_q
|
q => sq0_q
|
);
|
);
|
--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
|
--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
|
q2 : scfifo --! Debe ir registrada la salida.
|
q2 : scfifo --! Debe ir registrada la salida.
|
