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Line 31... |
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entity ap_n_dpc is
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entity ap_n_dpc is
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port (
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port (
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p0,p1,p2 : out std_logic_vector(31 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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ax : in std_logic_vector(31 downto 0);
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ax : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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Line 73... |
constant ssync_chain_max : integer :=27;
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constant ssync_chain_max : integer :=27;
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constant ssync_chain_min : integer :=2;
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constant ssync_chain_min : integer :=2;
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--! Tunnning delay
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--! Tunnning delay
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constant adder2_delay: integer := 1;
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constant adder2_delay: integer := 1;
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constant prod3_delay : integer := 2;
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constant adder1_delay : integer := 1;
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--!TBXSTART:FACTORS_N_ADDENDS
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--!TBXSTART:FACTORS_N_ADDENDS
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signal sfactor0 : std_logic_vector(31 downto 0);
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signal sfactor0 : std_logic_vector(31 downto 0);
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signal sfactor1 : std_logic_vector(31 downto 0);
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signal sfactor1 : std_logic_vector(31 downto 0);
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signal sfactor2 : std_logic_vector(31 downto 0);
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signal sfactor2 : std_logic_vector(31 downto 0);
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Line 276... |
process(clk,rst,sync_chain_1)
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process(clk,rst,sync_chain_1)
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begin
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begin
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
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ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
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p0 <= (others => '0');
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p1 <= (others => '0');
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p2 <= (others => '0');
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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for i in ssync_chain_max downto ssync_chain_min+1 loop
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for i in ssync_chain_max downto ssync_chain_min+1 loop
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ssync_chain(i) <= ssync_chain(i-1);
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ssync_chain(i) <= ssync_chain(i-1);
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end loop;
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end loop;
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ssync_chain(ssync_chain_min) <= sync_chain_1;
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ssync_chain(ssync_chain_min) <= sync_chain_1;
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--! Salida de los multiplicadores p0 p1 p2
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if ssync_chain(21)='1' then
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p0 <= sa0; -- El resultado quedara consignado en VZ1=BASE+1
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elsif ssync_chain(22)='1' then
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p1 <= sa0; -- El resutlado quedara consignado en VY1=BASE+2
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elsif ssync_chain(23)='1' then
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p2 <= sa0; -- El resultado quedara consignado en VX1=BASE+3
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end if;
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end if;
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end if;
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end process sync_chain_proc;
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end process sync_chain_proc;
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Line 417... |
ssumando4 <= az;
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ssumando4 <= az;
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ssumando5 <= bz;
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ssumando5 <= bz;
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if dcs(1)='1' then
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if dcs(1)='1' then
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sq2_d <= ssq32;
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sq2_d <= ssq32;
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sq2_w <= ssync_chain(22);
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sq2_w <= ssync_chain(22+adder1_delay);
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else
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else
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sq2_d <= sa1;
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sq2_d <= sa1;
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sq2_w <= ssync_chain(21);
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sq2_w <= ssync_chain(21+adder1_delay);
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end if;
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end if;
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sqr_dx <= sp3;
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sqr_dx <= sp3;
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sqr_dy <= sp4;
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sqr_dy <= sp4;
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sqr_dz <= sp5;
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sqr_dz <= sp5;
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Line 484... |
)
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)
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port map (
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port map (
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sclr => '0',
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sclr => '0',
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clock => clk,
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clock => clk,
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rdreq => ssync_chain(13),
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rdreq => ssync_chain(13),
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wrreq => ssync_chain(5+adder2_delay),
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wrreq => ssync_chain(5),
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data => sp2,
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data => sp2,
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q => sq0_q
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q => sq0_q
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);
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);
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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q2 : scfifo --! Debe ir registrada la salida.
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q2 : scfifo --! Debe ir registrada la salida.
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