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------------------------------------------------
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--! @file fadd32.vhd
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--! @brief RayTrac Floating Point Adder
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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-- RAYTRAC (FP BRANCH)
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-- Author Julian Andres Guarin
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-- fadd32.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.arithpack.all;
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--! Esta entidad recibe dos números en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
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--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
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entity fadd32long is
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port (
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clk,dpc : in std_logic;
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a32,b32 : in std_logic_vector(31 downto 0);
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c32 : out std_logic_vector(31 downto 0)
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);
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end entity;
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architecture fadd32long_arch of fadd32long is
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--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
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attribute altera_attribute : string;
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attribute altera_attribute of fadd32long_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
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--!TBXSTART:STAGE0
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signal s0delta : std_logic_vector(8 downto 0);
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signal s0a,s0b : std_logic_vector(31 downto 0); -- Float 32 bit
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--!TBXEND
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--!TBXSTART:STAGE1
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signal s1zero : std_logic;
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signal s1delta : std_logic_vector(5 downto 0);
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signal s1exp : std_logic_vector(7 downto 0);
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signal s1shifter,s1datab_8x : std_logic_vector(8 downto 0);
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signal s1pl,s1datab : std_logic_vector(17 downto 0);
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signal s1umantshift,s1umantfixed,s1postshift,s1xorslab : std_logic_vector(23 downto 0);
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signal s1ph : std_logic_vector(26 downto 0);
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--!TBXEND
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--!TBXSTART:STAGE2
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signal s2exp : std_logic_vector(7 downto 0);
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signal s2xorslab : std_logic_vector(23 downto 0);
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signal s2umantshift, s2mantfixed : std_logic_vector(24 downto 0);
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--!TBXEND
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--!TBXSTART:STAGE3
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signal s3exp : std_logic_vector(7 downto 0);
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signal s3mantfixed,s3mantshift : std_logic_vector (24 downto 0);
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--!TBXEND
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--!TBXSTART:STAGE4
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signal s4exp : std_logic_vector (7 downto 0);
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signal s4xorslab : std_logic_vector (24 downto 0);
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signal s4sresult : std_logic_vector (25 downto 0);
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--!TBXEND
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--!TBXSTART:STAGE5
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signal s5tokena,s5tokenb,s5tokenc : std_logic;
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signal s5token : std_logic_vector (2 downto 0);
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signal s5exp,s5factor : std_logic_vector (7 downto 0);
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signal s5factorhot9 : std_logic_vector (8 downto 0);
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signal s5factorhot24 : std_logic_vector (23 downto 0);
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signal s5result : std_logic_vector (25 downto 0);
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--!TBXEND
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--!TBXSTART:STAGE6
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signal s6exp,s6factor : std_logic_vector(7 downto 0);
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signal s6factorhot9,s6datab_4x : std_logic_vector(8 downto 0);
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signal s6pl,s6datab : std_logic_vector(17 downto 0);
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signal s6postshift : std_logic_vector(22 downto 0);
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signal s6result : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s6ph : std_logic_vector(26 downto 0);
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--!TBXEND
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--!TBXSTART:STAGE7
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signal s7sign : std_logic;
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signal s7exp,s7factor : std_logic_vector(7 downto 0);
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signal s7postshift : std_logic_vector(22 downto 0);
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--!TBXEND
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--! LPM_MULTIPLIER
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component lpm_mult
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generic (
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lpm_hint : string;
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lpm_pipeline : natural;
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lpm_representation : string;
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lpm_type : string;
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lpm_widtha : natural;
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lpm_widthb : natural;
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lpm_widthp : natural
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);
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port (
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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result : out std_logic_vector( lpm_widthp-1 downto 0 )
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);
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end component;
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begin
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process (clk)
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begin
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if clk'event and clk='1' then
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--! Debug Register.
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--! datab <= s1zero&"000"&x"00000"&s0b(30 downto 23);
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--! datab <= x"00"&s1exp&s0a(30 downto 23)&s0b(30 downto 23);
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--!Registro de entrada
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s0a <= a32;
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(30 downto 0) <= b32(30 downto 0);
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--!Etapa 0,Escoger el mayor exponente que sera el resultado desnormalizado, calcula cuanto debe ser el corrimiento de la mantissa con menor exponente y reorganiza los operandos, si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene. Zero check.
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--!signo,exponente,mantissa
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s1delta <= s0delta(8) & (s0delta(8) xor s0delta(4))&(s0delta(8) xor s0delta(3)) & s0delta(2 downto 0);
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if s0delta(8)='1' then
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s1exp <= s0b(30 downto 23);
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s1umantshift <= s0a(31)&s0a(22 downto 0);
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s1umantfixed <= s0b(31)&s0b(22 downto 0);
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if s0a(30 downto 23)=x"00" then
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s1zero <= '0';
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else
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s1zero <= '1';
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end if;
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else
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if s0b(30 downto 23)=x"00" then
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s1zero <= '0';
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else
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s1zero <= '1';
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end if;
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s1exp <= s0a(30 downto 23);
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s1umantshift <= s0b(31)&s0b(22 downto 0);
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s1umantfixed <= s0a(31)&s0a(22 downto 0);
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end if;
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--! Etapa 1: Denormalización de la mantissas.
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case s1delta(4 downto 3) is
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when "00" => s2umantshift <= s1umantshift(23)&s1postshift(23 downto 0);
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when "01" => s2umantshift <= s1umantshift(23)&x"00"&s1postshift(23 downto 8);
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when "10" => s2umantshift <= s1umantshift(23)&x"0000"&s1postshift(23 downto 16);
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when others => s2umantshift <= (others => '0');
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end case;
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s2mantfixed <= s1umantfixed(23) & ( ( ('1'&s1umantfixed(22 downto 0)) xor s1xorslab) + ( x"00000"&"000"&s1umantfixed(23) ) );
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s2exp <= s1exp;
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--! Etapa2: Signar la mantissa denormalizada.
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s3mantfixed <= s2mantfixed;
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s3mantshift <= s2umantshift(24)& ( ( s2umantshift(23 downto 0) xor s2xorslab) + ( x"00000"&"000"&s2umantshift(24) ) );
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s3exp <= s2exp;
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--! Etapa 3: Etapa 3 Realizar la suma, entre la mantissa corrida y la fija.
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s4sresult <= (s3mantshift(24)&s3mantshift)+(s3mantfixed(24)&s3mantfixed);
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s4exp <= s3exp;
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--! Etapa 4: Quitar el signo a la mantissa resultante.
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s5result <= s4sresult(25)&((s4sresult(24 downto 0) xor s4xorslab) +(x"000000"&s4sresult(25)));
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s5exp <= s4exp;
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--! Etapa 5: Codificar el corrimiento para la normalizacion de la mantissa resultante.
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s6result <= s5result;
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s6exp <= s5exp;
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s6factor <= s5factor;
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s6factorhot9 <= s5factorhot9;
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--! Etapa 6: Ejecutar el corrimiento de la mantissa.
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s7sign <= s6result(25);
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s7exp <= s6exp;
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s7factor <= not(s6factor)+1;
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s7postshift <= s6postshift;
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end if;
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end process;
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--! Etapa 7: Entregar el resultado.
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c32(31) <= s7sign;
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process(s7exp,s7postshift,s7factor)
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begin
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c32(30 downto 23) <= s7exp+s7factor;
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case s7factor(4 downto 3) is
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when "01" => c32(22 downto 0) <= s7postshift(14 downto 00)&x"00";
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when "10" => c32(22 downto 0) <= s7postshift(06 downto 00)&x"0000";
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when others => c32(22 downto 0) <= s7postshift;
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end case;
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end process;
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--! Combinatorial gremlin, Etapa 0 el corrimiento de la mantissa con menor exponente y reorganiza los operandos,\n
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--! si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene.
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s0delta <= ('0'&s0a(30 downto 23))-('0'&s0b(30 downto 23));
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--! Combinatorial Gremlin, Etapa 1 Codificar el factor de corrimiento de denormalizacion y denormalizar la mantissa no fija. Signar la mantissa que se queda fija.
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decodeshiftfactor:
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process (s1delta(2 downto 0))
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begin
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case s1delta(2 downto 0) is
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when "111" => s1shifter(8 downto 0) <= '0'&s1delta(5)&"00000"¬(s1delta(5))&'0';
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when "110" => s1shifter(8 downto 0) <= "00"&s1delta(5)&"000"¬(s1delta(5))&"00";
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when "101" => s1shifter(8 downto 0) <= "000"&s1delta(5)&'0'¬(s1delta(5))&"000";
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when "100" => s1shifter(8 downto 0) <= '0'&x"10";
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when "011" => s1shifter(8 downto 0) <= "000"¬(s1delta(5))&'0'&s1delta(5)&"000";
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when "010" => s1shifter(8 downto 0) <= "00"¬(s1delta(5))&"000"&s1delta(5)&"00";
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when "001" => s1shifter(8 downto 0) <= '0'¬(s1delta(5))&"00000"&s1delta(5)&'0';
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when others => s1shifter(8 downto 0) <= not(s1delta(5))&"0000000"&s1delta(5);
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end case;
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end process;
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s1datab <= s1zero&s1umantshift(22 downto 06);
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denormhighshiftermult:lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 0,
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lpm_representation => "UNSIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 9,
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lpm_widthb => 18,
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lpm_widthp => 27
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)
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port map (
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dataa => s1shifter,
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datab => s1datab,
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result => s1ph
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);
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s1datab_8x <= s1umantshift(5 downto 0)&"000";
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denormlowshiftermult:lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 0,
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lpm_representation => "UNSIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 9,
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lpm_widthb => 9,
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lpm_widthp => 18
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)
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port map (
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dataa => s1shifter,
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datab(8 downto 0) => s1datab_8x,
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result => s1pl
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);
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s1postshift(23 downto 7) <= s1ph(25 downto 9);
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s1postshift(06 downto 0) <= s1ph(08 downto 2) or s1pl(17 downto 11);
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s1xorslab(23 downto 0) <= (others => s1umantfixed(23));
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--! Combinatorial Gremlin, Etapa 2: Signar la mantissa denormalizada.
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s2xorslab <= (others => s2umantshift(24));
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--! Combinatorial Gremlin, Etapa 4: Quitar el signo de la mantissa resultante.
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s4xorslab <= (others => s4sresult(25));
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--! Combinatorial Gremlin, Etapa 5: Codificar el factor de normalizacion de la mantissa resultante.
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normalizerdecodeshift:
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process (s5result,s5factorhot24,s5token,s5tokena,s5tokenb,s5tokenc,s5factorhot9)
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begin
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s5tokena <= not(s5result(24));
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s5tokenb <= not(s5result(24));
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s5tokenc <= not(s5result(24));
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s5factor(7 downto 5) <= (others => s5result(24));
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s5factorhot24 <= x"000000";
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for i in 23 downto 16 loop
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if s5result(i)='1' then
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s5factorhot24(23-i) <= s5tokena;
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s5tokenb <= '0';
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s5tokenc <= '0';
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exit;
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end if;
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end loop;
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for i in 15 downto 8 loop
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if s5result(i)='1' then
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s5factorhot24(23-i) <= s5tokenb;
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s5tokenc <= '0';
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exit;
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end if;
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end loop;
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for i in 7 downto 0 loop
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if s5result(i)='1' then
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s5factorhot24(23-i) <= s5tokenc;
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exit;
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end if;
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end loop;
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s5token <=s5tokena&s5tokenb&s5tokenc;
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case (s5token) is
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when "100" => s5factor(4 downto 3) <= "00";
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when "110" => s5factor(4 downto 3) <= "01";
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when "111" => s5factor(4 downto 3) <= "10";
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when others => s5factor(4 downto 3) <= (others => s5result(24));
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end case;
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s5factorhot9 <= (s5factorhot24(7 downto 0)or s5factorhot24(15 downto 8)or s5factorhot24(23 downto 16)) & s5result(24);
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case s5factorhot9 is
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when "100000000" => s5factor(2 downto 0) <= "111";
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when "010000000" => s5factor(2 downto 0) <= "110";
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when "001000000" => s5factor(2 downto 0) <= "101";
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when "000100000" => s5factor(2 downto 0) <= "100";
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when "000010000" => s5factor(2 downto 0) <= "011";
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when "000001000" => s5factor(2 downto 0) <= "010";
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when "000000100" => s5factor(2 downto 0) <= "001";
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when "000000010" => s5factor(2 downto 0) <= "000";
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when others => s5factor (2 downto 0) <= (others => s5result(24));
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end case;
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end process;
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--! Etapa 6: Ejecutar el corrimiento para normalizar la mantissa.
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s6datab <= s6result(24 downto 7);
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normhighshiftermult:lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 0,
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lpm_representation => "UNSIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 9,
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lpm_widthb => 18,
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lpm_widthp => 27
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)
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port map (
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dataa => s6factorhot9,
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datab => s6datab,
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result => s6ph
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);
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s6datab_4x <= s6result(06 downto 0)&"00";
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normlowshiftermult:lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 0,
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lpm_representation => "UNSIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 9,
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lpm_widthb => 9,
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lpm_widthp => 18
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)
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port map (
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dataa => s6factorhot9,
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datab => s6datab_4x,
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result => s6pl
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);
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s6postshift(22 downto 15) <= s6ph(16 downto 09);
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s6postshift(14 downto 06) <= s6ph(08 downto 00) + s6pl(17 downto 09);
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s6postshift(05 downto 00) <= s6pl(08 downto 03);
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end architecture;
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No newline at end of file
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No newline at end of file
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