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--! @file arithblock.vhd
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--! @brief Bloque Aritmético de 4 sumadores y 6 multiplicadores.
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- memblock.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all;
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use work.arithpack.all;
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entity arithblock is
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port (
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clk : in std_logic;
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rst : in std_logic;
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sign : in std_logic;
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factor0 : in std_logic_vector(31 downto 0);
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factor1 : in std_logic_vector(31 downto 0);
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factor2 : in std_logic_vector(31 downto 0);
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factor3 : in std_logic_vector(31 downto 0);
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factor4 : in std_logic_vector(31 downto 0);
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factor5 : in std_logic_vector(31 downto 0);
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factor6 : in std_logic_vector(31 downto 0);
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factor7 : in std_logic_vector(31 downto 0);
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factor8 : in std_logic_vector(31 downto 0);
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factor9 : in std_logic_vector(31 downto 0);
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factor10 : in std_logic_vector(31 downto 0);
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factor11 : in std_logic_vector(31 downto 0);
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--factor : in vectorblock06;
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sumando0 : in std_logic_vector(31 downto 0);
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sumando1 : in std_logic_vector(31 downto 0);
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sumando2 : in std_logic_vector(31 downto 0);
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sumando3 : in std_logic_vector(31 downto 0);
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sumando4 : in std_logic_vector(31 downto 0);
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sumando5 : in std_logic_vector(31 downto 0);
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--add32blki : in vectorblock06;
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a0 : out std_logic_vector(31 downto 0);
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a1 : out std_logic_vector(31 downto 0);
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a2 : out std_logic_vector(31 downto 0);
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--add32blko : out vectorblock03;
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p0 : out std_logic_vector(31 downto 0);
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p1 : out std_logic_vector(31 downto 0);
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p2 : out std_logic_vector(31 downto 0);
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p3 : out std_logic_vector(31 downto 0);
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p4 : out std_logic_vector(31 downto 0);
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p5 : out std_logic_vector(31 downto 0);
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--p : out vectorblock06;
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sq32o : out std_logic_vector(31 downto 0);
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inv32o : out std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arithblock_arch of arithblock is
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--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
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attribute altera_attribute : string;
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attribute altera_attribute of arithblock_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
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signal sadd32blko_01 : std_logic_vector(31 downto 0);
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signal ssq32o : std_logic_vector(31 downto 0);
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--! Componentes Aritméticos
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component fadd32long
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port (
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clk : in std_logic;
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dpc : in std_logic;
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a32 : in std_logic_vector(31 downto 0);
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b32 : in std_logic_vector(31 downto 0);
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c32 : out std_logic_vector(31 downto 0)
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);
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end component;
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component fmul32
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port (
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factor0 : in std_logic_vector(31 downto 0);
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factor1 : in std_logic_vector(31 downto 0);
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factor2 : in std_logic_vector(31 downto 0);
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factor3 : in std_logic_vector(31 downto 0);
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factor4 : in std_logic_vector(31 downto 0);
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factor5 : in std_logic_vector(31 downto 0);
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factor6 : in std_logic_vector(31 downto 0);
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factor7 : in std_logic_vector(31 downto 0);
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factor8 : in std_logic_vector(31 downto 0);
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factor9 : in std_logic_vector(31 downto 0);
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factor10: in std_logic_vector(31 downto 0);
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factor11: in std_logic_vector(31 downto 0);
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p0: out std_logic_vector(31 downto 0);
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p1: out std_logic_vector(31 downto 0);
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p2: out std_logic_vector(31 downto 0);
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p3: out std_logic_vector(31 downto 0);
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p4: out std_logic_vector(31 downto 0);
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p5: out std_logic_vector(31 downto 0);
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);
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end component;
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--! Bloque de Raiz Cuadrada
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component sqrt32
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port (
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clk : in std_logic;
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rd32: in std_logic_vector(31 downto 0);
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sq32: out std_logic_vector(31 downto 0)
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);
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end component;
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--! Bloque de Inversores.
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component invr32
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port (
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clk : in std_logic;
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dvd32 : in std_logic_vector(31 downto 0);
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qout32 : out std_logic_vector(31 downto 0)
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);
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end component;
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begin
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sq32o <= ssq32o;
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a1 <= sadd32blko_01;
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--!TBXINSTANCESTART
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adder_i_0 : fadd32long
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port map (
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clk => clk,
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dpc => sign,
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a32 => sumando0,
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b32 => sumando1,
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c32 => a0
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);
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--!TBXINSTANCESTART
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adder_i_1 : fadd32long
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port map (
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clk => clk,
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dpc => sign,
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a32 => sumando2,
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b32 => sumando3,
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c32 => sadd32blko_01
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);
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--!TBXINSTANCESTART
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adder_i_2 : fadd32long
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port map (
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clk => clk,
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dpc => sign,
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a32 => sumando4,
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b32 => sumando5,
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c32 => a2
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);
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--!TBXINSTANCESTART
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mul_i_0 : fmul32
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port map (
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clk => clk,
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factor0 => factor0,
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factor1 => factor1,
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factor2 => factor2,
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factor3 => factor3,
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factor4 => factor4,
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factor5 => factor5,
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factor6 => factor6,
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factor7 => factor7,
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factor8 => factor8,
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factor9 => factor9,
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factor10 => factor10,
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factor11 => factor11,
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p0 => p0,
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p1 => p1,
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p2 => p2,
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p3 => p3,
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p4 => p4,
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p5 => p5
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);
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--!TBXINSTANCESTART
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square_root : sqrt32
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port map (
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clk => clk,
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rd32 => sadd32blko_01,
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sq32 => ssq32o
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);
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--!TBXINSTANCESTART
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inversion_block : invr32
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port map (
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clk => clk,
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dvd32 => ssq32o,
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qout32 => inv32o
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);
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end architecture;
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