URL
https://opencores.org/ocsvn/raytrac/raytrac/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 238 |
Rev 239 |
Line 96... |
Line 96... |
c32 : out std_logic_vector(31 downto 0)
|
c32 : out std_logic_vector(31 downto 0)
|
);
|
);
|
end component;
|
end component;
|
component fmul32
|
component fmul32
|
port (
|
port (
|
|
clk : std_logic;
|
factor0 : in std_logic_vector(31 downto 0);
|
factor0 : in std_logic_vector(31 downto 0);
|
factor1 : in std_logic_vector(31 downto 0);
|
factor1 : in std_logic_vector(31 downto 0);
|
factor2 : in std_logic_vector(31 downto 0);
|
factor2 : in std_logic_vector(31 downto 0);
|
factor3 : in std_logic_vector(31 downto 0);
|
factor3 : in std_logic_vector(31 downto 0);
|
factor4 : in std_logic_vector(31 downto 0);
|
factor4 : in std_logic_vector(31 downto 0);
|
Line 113... |
Line 114... |
p0: out std_logic_vector(31 downto 0);
|
p0: out std_logic_vector(31 downto 0);
|
p1: out std_logic_vector(31 downto 0);
|
p1: out std_logic_vector(31 downto 0);
|
p2: out std_logic_vector(31 downto 0);
|
p2: out std_logic_vector(31 downto 0);
|
p3: out std_logic_vector(31 downto 0);
|
p3: out std_logic_vector(31 downto 0);
|
p4: out std_logic_vector(31 downto 0);
|
p4: out std_logic_vector(31 downto 0);
|
p5: out std_logic_vector(31 downto 0);
|
p5: out std_logic_vector(31 downto 0)
|
|
|
);
|
);
|
end component;
|
end component;
|
--! Bloque de Raiz Cuadrada
|
--! Bloque de Raiz Cuadrada
|
component sqrt32
|
component sqrt32
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.