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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.math_real.all;
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No newline at end of file
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No newline at end of file
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library std;
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use std.textio.all;
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--! Memory Compiler Library
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library altera_mf;
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use altera_mf.all;
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library lpm;
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use lpm.all;
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package arithpack is
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--! Estados para la maquina de estados.
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type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
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--! Estados para el controlador de interrupciones.
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type iCtrlState is (WAITING_FOR_A_RFULL_EVENT,INHIBIT_RFULL_INT);
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--! Float data blocks
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constant floatwidth : integer := 32;
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--! Control de tamaños de memoria.
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constant widthadmemblock : integer := 9;
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--! Reducció de memoria por mitades
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constant memoryreduction : integer := 1;
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subtype xfloat32 is std_logic_vector(31 downto 0);
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type v3f is array(02 downto 0) of xfloat32;
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--! Constantes para definir
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--!type vectorblock12 is array (11 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock12 is array (11 downto 0) of xfloat32;
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type vectorblock08 is array (07 downto 0) of xfloat32;
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type vectorblock06 is array (05 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock04 is array (03 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock03 is array (02 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1-memoryreduction downto 0);
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--! Constante de reseteo
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constant rstMasterValue : std_logic :='0';
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--! Constantes periodicas.
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constant tclk : time := 20 ns;
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constant tclk_2 : time := tclk/2;
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constant tclk_4 : time := tclk/4;
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component raytrac
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port (
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clk : in std_logic;
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rst : in std_logic;
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--! Señal de lectura de alguna de las colas de resultados.
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rd : in std_logic;
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--! Señal de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.
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wr : in std_logic;
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--! Direccion de escritura o lectura
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add : in std_logic_vector (12 downto 0);
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--! datos de entrada
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d : in std_logic_vector (31 downto 0);
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--! Interrupciones
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int : out std_logic;
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--! Salidas
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q : out std_logic_vector (31 downto 0)
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);
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end component;
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--! Componentes Aritméticos
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component fadd32
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port (
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clk : in std_logic;
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dpc : in std_logic;
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a32 : in xfloat32;
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b32 : in xfloat32;
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c32 : out xfloat32
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);
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end component;
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component fmul32
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port (
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clk : in std_logic;
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a32 : in xfloat32;
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b32 : in xfloat32;
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p32 : out xfloat32
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);
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end component;
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--! Contadores para la máquina de estados.
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component customCounter
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generic (
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EOBFLAG : string ;
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ZEROFLAG : string ;
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BACKWARDS : string ;
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EQUALFLAG : string ;
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subwidth : integer;
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width : integer
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);
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port (
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clk,rst,go,set : in std_logic;
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setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);
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zero_flag,eob_flag,eq_flag : out std_logic;
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count : out std_logic_vector(width-1 downto 0)
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);
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end component;
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--! LPM_MULTIPLIER
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component lpm_mult
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generic (
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lpm_hint : string;
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lpm_pipeline : natural;
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lpm_representation : string;
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lpm_type : string;
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lpm_widtha : natural;
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lpm_widthb : natural;
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lpm_widthp : natural
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);
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port (
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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result : out std_logic_vector( lpm_widthp-1 downto 0 )
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);
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end component;
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--! LPM Memory Compiler.
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component scfifo
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generic (
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add_ram_output_register :string;
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almost_full_value :natural;
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allow_rwcycle_when_full :string;
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intended_device_family :string;
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lpm_hint :string;
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lpm_numwords :natural;
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lpm_showahead :string;
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lpm_type :string;
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lpm_width :natural;
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lpm_widthu :natural;
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overflow_checking :string;
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underflow_checking :string;
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use_eab :string
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);
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port(
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rdreq : in std_logic;
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aclr : in std_logic;
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empty : out std_logic;
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clock : in std_logic;
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q : out std_logic_vector(lpm_width-1 downto 0);
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wrreq : in std_logic;
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data : in std_logic_vector(lpm_width-1 downto 0);
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almost_full : out std_logic;
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full : out std_logic
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);
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end component;
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component altsyncram
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generic (
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address_aclr_b : string;
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address_reg_b : string;
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clock_enable_input_a : string;
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clock_enable_input_b : string;
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clock_enable_output_b : string;
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intended_device_family : string;
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lpm_type : string;
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numwords_a : natural;
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numwords_b : natural;
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operation_mode : string;
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outdata_aclr_b : string;
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outdata_reg_b : string;
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power_up_uninitialized : string;
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ram_block_type : string;
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rdcontrol_reg_b : string;
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read_during_write_mode_mixed_ports : string;
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widthad_a : natural;
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widthad_b : natural;
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width_a : natural;
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width_b : natural;
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width_byteena_a : natural
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);
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port (
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wren_a : in std_logic;
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clock0 : in std_logic;
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address_a : in std_logic_vector(widthadmemblock-1-memoryreduction downto 0);
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address_b : in std_logic_vector(widthadmemblock-1-memoryreduction downto 0);
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rden_b : in std_logic;
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q_b : out std_logic_vector(31 downto 0);
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data_a : in std_logic_vector(31 downto 0)
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);
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end component;
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--! Maquina de Estados.
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component sm
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port (
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--! Señales normales de secuencia.
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clk,rst: in std_logic;
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--! Vector con las instrucción codficada
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instrQq:in std_logic_vector(31 downto 0);
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--! Señal de cola vacia.
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instrQ_empty:in std_logic;
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adda,addb:out std_logic_vector (8 downto 0);
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sync_chain_0,instrRdAckd:out std_logic;
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full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
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--! End Of Instruction Event
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eoi : out std_logic;
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--! DataPath Control uca code.
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dpc_uca : out std_logic_vector (2 downto 0);
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state : out macState
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);
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end component;
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--! Maquina de Interrupciones
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component im
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generic (
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num_events : integer ;
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cycles_to_wait : integer
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);
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port (
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clk,rst: in std_logic;
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rfull_event: in std_logic; --! full results queue events
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eoi_event: in std_logic; --! end of instruction related events
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int: out std_logic;
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state: out iCtrlState
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);
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end component;
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--! Bloque de memorias
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component memblock
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port (
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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instrfifo_rd : in std_logic;
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resultfifo_wr: in std_logic_vector(8-1 downto 0);
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instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(3 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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int_d : in vectorblock08;
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status_register : in std_logic_vector(3 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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int_q : out vectorblock12;
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
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);
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end component;
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--! Bloque decodificacion DataPath Control.
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component dpc
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port (
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clk,rst : in std_logic;
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paraminput : in vectorblock06; --! Vectores A,B
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prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.
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add32blko : in vectorblock03; --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (floatwidth-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x19_q : in std_logic_vector (03*floatwidth-1 downto 0);--! Salida de la cola intermedia.
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fifo32x09_q : in std_logic_vector (floatwidth-1 downto 0);--! Salida de las colas de producto punto.
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d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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sqr32blki,inv32blki : out std_logic_vector (floatwidth-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x19_d : out std_logic_vector (03*floatwidth-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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q0_32x03_d : out std_logic_vector (floatwidth-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out vectorblock06; --! Entrada de los 6 sumandos del bloque de 3 sumadores.
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resw : out std_logic_vector (3 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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q0_32x03_w : out std_logic;
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q1xyz_32x20_w : out std_logic;
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q0_32x03_r : out std_logic;
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q1xyz_32x20_r : out std_logic;
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resf_vector : in std_logic_vector (3 downto 0); --! Entradas de la señal de full de las colas de resultados.
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resultoutput : out vectorblock04 --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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end component;
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
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port (
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clk : in std_logic;
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rst : in std_logic;
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dpc : in std_logic;
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f : in vectorblock12;
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a : in vectorblock08;
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s : out vectorblock04;
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p : out vectorblock06
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);
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end component;
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--! Bloque de Raiz Cuadrada
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component sqrt32
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port (
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clk : in std_logic;
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rd32: in xfloat32;
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sq32: out xfloat32
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);
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end component;
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--! Bloque de Inversores.
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component invr32
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port (
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clk : in std_logic;
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dvd32 : in xfloat32;
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qout32 : out xfloat32
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);
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end component;
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type apCamera is record
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resx,resy : integer;
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width,height : real;
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dist : real;
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end record;
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--! Función que convierte un std_logic_vector en un numero entero
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function ap_slv2int(sl:std_logic_vector) return integer;
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--! Función que convierte un número flotante IEE754 single float, en un número std_logic_vector.
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function ap_fp2slv (f:real) return std_logic_vector;
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--! Función que convierte un número std_logic_vector en un ieee754 single float.
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function ap_slv2fp (sl:std_logic_vector) return real;
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--! Función que devuelve un vector en punto flotante IEEE754 a través de un
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function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;
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--! Función que devuelve una cadena con el número flotante IEEE 754 ó a una cadena de cifras hexadecimales.
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procedure ap_slvf2string(l:inout line;sl:std_logic_vector);
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procedure ap_slv2hex (l:inout line;h:in std_logic_vector) ;
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--! Función que devuelve una cadena con el estado de macState.
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procedure ap_macState2string(l:inout line;s:in macState);
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--! Función que convierte un array de 2 std_logic_vectors que contienen un par de direcciones en string
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procedure ap_vnadd022string(l:inout line; va2:in vectorblockadd02);
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--! Función que devuelve una cadena de caracteres con el estado de la maquina de estados que controla las interrupciones
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procedure ap_iCtrlState2string(l:inout line;i:in iCtrlState) ;
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--! Función que devuelve una cadena con los componentes de un vector R3 en punto flotante IEEE754
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procedure ap_v3f2string(l:inout line;v:in v3f);
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procedure ap_xfp032string(l:inout line;vb03:in vectorblock03);
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--! Función que formatea una instrucción
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function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector;
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--! Función que devuelve una cadena de caracteres de un solo caracter con el valor de un bit std_logic
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procedure ap_sl2string(l:inout line;s:std_logic);
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--! Procedimiento para mostrar vectores en forma de arreglos de flotantes
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procedure ap_xfp122string(l:inout line;vb12:in vectorblock12);
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procedure ap_xfp082string(l:inout line;vb08:in vectorblock08);
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procedure ap_xfp062string(l:inout line;vb06:in vectorblock06);
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procedure ap_xfp042string(l:inout line;vb04:in vectorblock04);
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procedure ap_xfp022string(l:inout line;vb02:in vectorblock02);
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end package;
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package body arithpack is
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procedure ap_xfp022string(l:inout line; vb02:in vectorblock02) is
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begin
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for i in 01 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" "));
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ap_slvf2string(l,vb02(i));
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end loop;
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end procedure;
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procedure ap_xfp122string(l:inout line; vb12:in vectorblock12) is
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begin
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for i in 11 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" "));
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ap_slvf2string(l,vb12(i));
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end loop;
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end procedure;
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procedure ap_xfp082string(l:inout line; vb08:in vectorblock08) is
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begin
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for i in 07 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" "));
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ap_slvf2string(l,vb08(i));
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end loop;
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end procedure;
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procedure ap_xfp062string(l:inout line; vb06:in vectorblock06) is
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begin
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for i in 05 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" "));
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ap_slvf2string(l,vb06(i));
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end loop;
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end procedure;
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procedure ap_xfp042string(l:inout line; vb04:in vectorblock04) is
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begin
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for i in 03 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" "));
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ap_slvf2string(l,vb04(i));
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end loop;
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end procedure;
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procedure ap_sl2string(l:inout line; s:in std_logic)is
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variable tmp:string(1 to 1);
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begin
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case s is
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when '1' =>
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tmp:="1";
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when '0' =>
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tmp:="0";
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when 'U' =>
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tmp:="U";
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when 'X' =>
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tmp:="X";
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when 'Z' =>
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tmp:="Z";
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when 'W' =>
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tmp:="W";
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when 'L' =>
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tmp:="L";
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when 'H' =>
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tmp:="H";
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when others =>
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tmp:="-"; -- Don't care
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end case;
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write(l,string'(" "));
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write(l,string'(tmp));
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write(l,string'(" "));
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end procedure;
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function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector is
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alias aco : std_logic_vector (4 downto 0) is ac_o;
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alias acf : std_logic_vector (4 downto 0) is ac_f;
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alias bdo : std_logic_vector (4 downto 0) is bd_o;
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alias bdf : std_logic_vector (4 downto 0) is bd_f;
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variable ins : std_logic_vector (31 downto 0);
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alias it : string (1 to 3) is i;
|
|
begin
|
|
|
|
case it is
|
|
when "mag" =>
|
|
ins(31 downto 29) := "100";
|
|
ins(04 downto 00) := '1'&x"8";
|
|
when "nrm" =>
|
|
ins(31 downto 29) := "110";
|
|
ins(04 downto 00) := '1'&x"d";
|
|
when "add" =>
|
|
ins(31 downto 29) := "001";
|
|
ins(04 downto 00) := '0'&x"a";
|
|
when "sub" =>
|
|
ins(31 downto 29) := "011";
|
|
ins(04 downto 00) := '0'&x"a";
|
|
when "dot" =>
|
|
ins(31 downto 29) := "000";
|
|
ins(04 downto 00) := '1'&x"7";
|
|
when "crs" =>
|
|
ins(31 downto 29) := "010";
|
|
ins(04 downto 00) := '0'&x"e";
|
|
when others =>
|
|
ins(31 downto 29) := "111";
|
|
ins(04 downto 00) := '0'&x"5";
|
|
end case;
|
|
ins(28 downto 24) := aco;
|
|
ins(23 downto 19) := acf;
|
|
ins(18 downto 14) := bdo;
|
|
ins(13 downto 09) := bdf;
|
|
ins(08) := comb;
|
|
ins(07 downto 05) := "000";
|
|
return ins;
|
|
|
|
|
|
end function;
|
|
|
|
|
|
|
|
procedure ap_v3f2string(l:inout line;v:in v3f) is
|
|
begin
|
|
write(l,string'("[X]"));
|
|
write(l,string'(" "));
|
|
ap_slvf2string(l,v(2));
|
|
write(l,string'("[Y]"));
|
|
write(l,string'(" "));
|
|
ap_slvf2string(l,v(1));
|
|
write(l,string'("[Z]"));
|
|
write(l,string'(" "));
|
|
ap_slvf2string(l,v(0));
|
|
end procedure;
|
|
procedure ap_xfp032string(l:inout line;vb03:in vectorblock03) is
|
|
begin
|
|
write(l,string'("[X]"));
|
|
write(l,string'(" "));
|
|
ap_slvf2string(l,vb03(2));
|
|
write(l,string'("[Y]"));
|
|
write(l,string'(" "));
|
|
ap_slvf2string(l,vb03(1));
|
|
write(l,string'("[Z]"));
|
|
write(l,string'(" "));
|
|
ap_slvf2string(l,vb03(0));
|
|
end procedure;
|
|
|
|
procedure ap_iCtrlState2string(l:inout line;i:in iCtrlState) is
|
|
variable tmp:string (1 to 9);
|
|
begin
|
|
|
|
write(l,string'("<< "));
|
|
case i is
|
|
when WAITING_FOR_A_RFULL_EVENT =>
|
|
tmp:="WAIT_RF_EVNT";
|
|
when INHIBIT_RFULL_INT =>
|
|
tmp:="INHB_RF_INT";
|
|
when others =>
|
|
tmp:="ILGL__VAL";
|
|
end case;
|
|
write(l,string'(tmp));
|
|
write(l,string'(" >>"));
|
|
|
|
end procedure;
|
|
|
|
procedure ap_vnadd022string(l:inout line;va2:in vectorblockadd02) is
|
|
begin
|
|
|
|
write(l,string'("<<[1] "));
|
|
ap_slv2hex(l,va2(1));
|
|
write(l,string'(" [0] "));
|
|
ap_slv2hex(l,va2(0));
|
|
write(l,string'(" >>"));
|
|
|
|
end procedure;
|
|
|
|
procedure ap_macState2string(l:inout line;s:in macState) is
|
|
variable tmp:string (1 to 6);
|
|
begin
|
|
|
|
write(l,string'("<< "));
|
|
case s is
|
|
when LOAD_INSTRUCTION =>
|
|
tmp:="LD_INS";
|
|
when FLUSH_ARITH_PIPELINE =>
|
|
tmp:="FL_ARP";
|
|
when EXECUTE_INSTRUCTION =>
|
|
tmp:="EX_INS";
|
|
when others =>
|
|
tmp:="HEL_ON";
|
|
end case;
|
|
write(l,string'(tmp));
|
|
write(l,string'(" >>"));
|
|
|
|
end procedure;
|
|
|
|
constant hexchars : string (1 to 16) := "0123456789ABCDEF";
|
|
procedure ap_slv2hex (l:inout line;h:in std_logic_vector) is
|
|
variable index_high,index_low,highone,nc : integer;
|
|
begin
|
|
highone := h'high-h'low;
|
|
nc:=0;
|
|
for i in h'high downto h'low loop
|
|
if h(i)/='0' and h(i)/='1' then
|
|
nc:=1;
|
|
end if;
|
|
end loop;
|
|
|
|
if nc=1 then
|
|
for i in h'high downto h'low loop
|
|
ap_sl2string(l,h(i));
|
|
end loop;
|
|
else
|
|
for i in (highone)/4 downto 0 loop
|
|
index_low:=i*4;
|
|
if (index_low+3)>highone then
|
|
index_high := highone;
|
|
else
|
|
index_high := i*4+3;
|
|
end if;
|
|
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high+h'low downto index_low+h'low))));
|
|
end loop;
|
|
end if;
|
|
end procedure;
|
|
|
|
function ap_slv2int (sl:std_logic_vector) return integer is
|
|
alias s : std_logic_vector (sl'high downto sl'low) is sl;
|
|
variable i : integer;
|
|
begin
|
|
i:=0;
|
|
for index in s'high downto s'low loop
|
|
if s(index)='1' then
|
|
i:=i*2+1;
|
|
else
|
|
i:=i*2;
|
|
end if;
|
|
end loop;
|
|
return i;
|
|
|
|
end function;
|
|
function ap_fp2slv (f:real) return std_logic_vector is
|
|
variable faux : real;
|
|
variable sef : std_logic_vector (31 downto 0);
|
|
begin
|
|
--! Signo
|
|
if (f<0.0) then
|
|
sef(31) := '1';
|
|
faux:=f*(-1.0);
|
|
else
|
|
sef(31) := '0';
|
|
faux:=f;
|
|
end if;
|
|
|
|
--! Exponente
|
|
sef(30 downto 23) := conv_std_logic_vector(127+integer(floor(log(faux,2.0))),8);
|
|
|
|
--! Fraction
|
|
faux :=faux/(2.0**real(floor(log(faux,2.0))));
|
|
faux := faux - 1.0;
|
|
|
|
sef(22 downto 0) := conv_std_logic_vector(integer(faux*(2.0**23.0)),23);
|
|
|
|
return sef;
|
|
|
|
end function;
|
|
|
|
function ap_slv2fp(sl:std_logic_vector) return real is
|
|
variable frc:integer;
|
|
alias s: std_logic_vector(31 downto 0) is sl;
|
|
variable f,expo: real;
|
|
|
|
begin
|
|
|
|
|
|
expo:=real(ap_slv2int(s(30 downto 23)) - 127);
|
|
expo:=(2.0)**(expo);
|
|
frc:=ap_slv2int('1'&s(22 downto 0));
|
|
f:=real(frc)*(2.0**(-23.0));
|
|
f:=f*real(expo);
|
|
|
|
if s(31)='1' then
|
|
return -f;
|
|
else
|
|
return f;
|
|
end if;
|
|
|
|
|
|
|
|
|
|
end function;
|
|
|
|
function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f is
|
|
|
|
|
|
variable dx,dy : real;
|
|
variable v : v3f;
|
|
begin
|
|
|
|
dx := cam.width/real(cam.resx);
|
|
dy := cam.height/real(cam.resy);
|
|
|
|
--! Eje Z: Tomando el dedo índice de la mano derecha, este eje queda apuntando en la direcci&on en la que mira la cámara u observador siempre.
|
|
v(0):=ap_fp2slv(cam.dist);
|
|
|
|
--! Eje X: Tomando el dedo corazón de la mano derecha, este eje queda apuntando a la izquierda del observador, desde el observador.
|
|
v(2):=ap_fp2slv(dx*real(cam.resx)*0.5-real(x)*dx-dx*0.5);
|
|
|
|
--! Eje Y: Tomando el dedo pulgar de la mano derecha, este eje queda apuntando hacia arriba del observador, desde el observador.
|
|
v(1):=ap_fp2slv(dy*real(cam.resy)*0.5-real(y)*dy-dy*0.5);
|
|
|
|
return v;
|
|
|
|
end function;
|
|
|
|
procedure ap_slvf2string(l:inout line;sl:std_logic_vector) is
|
|
alias f: std_logic_vector(31 downto 0) is sl;
|
|
variable r: real;
|
|
|
|
begin
|
|
|
|
r:=ap_slv2fp(f);
|
|
write(l,string'(real'image(r)));
|
|
write(l,string'(" [ s:"));
|
|
ap_slv2hex(l,f(31 downto 31));
|
|
write(l,string'(" f: "));
|
|
ap_slv2hex(l,f(30 downto 23));
|
|
write(l,string'(" m: "));
|
|
ap_slv2hex(l,f(22 downto 00));
|
|
write(l,string'(" ]"));
|
|
|
|
end procedure;
|
|
|
|
|
|
|
|
|
|
end package body;
|
No newline at end of file
|
No newline at end of file
|
