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package arithpack is
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package arithpack is
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--!Constantes usadas por los RTLs
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--!Constantes usadas por los RTLs
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constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant sc : integer := 03;
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constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant qsc: integer := 03;
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constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
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constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
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constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
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constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
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constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
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constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
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constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
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constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
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constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
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constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
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constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
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constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
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constant index_control_register : integer := 00;
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constant index_start_address_r : integer := 01;
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constant index_end_address_r : integer := 02;
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constant index_start_address_w : integer := 03;
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constant index_end_address_w : integer := 04;
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constant index_scratch_register : integer := 05;
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--! Máquina de estados.
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--! Control de tamaños de memoria.
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constant widthadmemblock : integer := 9;
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subtype xfloat32 is std_logic_vector(31 downto 0);
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subtype xfloat32 is std_logic_vector(31 downto 0);
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type v3f is array(02 downto 0) of xfloat32;
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type v3f is array(02 downto 0) of xfloat32;
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--! Constantes para definir bloques de valores de 32 bits single float
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--! Constantes para definir bloques de valores de 32 bits single float
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constant tclk : time := 20 ns;
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constant tclk : time := 20 ns;
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constant tclk_2 : time := tclk/2;
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constant tclk_2 : time := tclk/2;
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constant tclk_4 : time := tclk/4;
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constant tclk_4 : time := tclk/4;
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component raytrac
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port (
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clk : in std_logic;
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rst : in std_logic;
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--! Interface Avalon Master
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address_master : out std_logic_vector(31 downto 0);
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begintransfer : out std_logic;
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read_master : out std_logic;
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readdata_master : in std_logic_vector (31 downto 0);
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write_master : out std_logic;
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writedata_master: out std_logic_vector (31 downto 0);
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waitrequest : in std_logic_vector;
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readdatavalid_m : in std_logic_vector;
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--! Interface Avalon Slave
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address_slave : in std_logic_vector(3 downto 0);
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read_slave : in std_logic;
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readdata_slave : in std_logic_vector(31 downto 0);
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write_slave : in std_logic;
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writedata_slave : in std_logic_vector(31 downto 0);
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readdatavalid_s : out std_logic;
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--! Interface Interrupt Sender
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irq : out std_logic
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);
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end component;
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component raytrac_control
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port (
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--! Señales normales de secuencia.
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clk: in std_logic;
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rst: in std_logic;
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--! Interface Avalon Master
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begintransfer : out std_logic;
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address_master : out std_logic_vector(31 downto 0);
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read_master : out std_logic;
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write_master : out std_logic;
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waitrequest : in std_logic;
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readdatavalid_m : in std_logic;
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--! Interface Avalon Slave
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address_slave : in std_logic_vector(3 downto 0);
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read_slave : in std_logic;
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readdata_slave : out std_logic_vector(31 downto 0);
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write_slave : in std_logic;
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writedata_slave : in std_logic_vector(31 downto 0);
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readdatavalid_s : out std_logic;
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--! Interface Interrupt Sender
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irq : out std_logic;
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--! Señales de Control (Memblock)
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go : out std_logic;
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comb : out std_logic;
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load : out std_logic;
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load_chain : out std_logic_vector(1 downto 0);
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qparams_e : in std_logic;
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qresult_e : in std_logic_vector(3 downto 0);
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--! Señles de Control de Datapath (DPC)
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qparams_q : in xfloat32;
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d : out std_logic;
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c : out std_logic;
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s : out std_logic;
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qresult_sel : out std_logic_vector(1 downto 0)
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);
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end component;
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--! Bloque de memorias
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component memblock
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port (
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--!Entradas de Control
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clk : in std_logic;
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rst : in std_logic;
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go : in std_logic;
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comb : in std_logic;
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load : in std_logic;
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load_chain : in std_logic_vector(1 downto 0);
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--! Cola de parámetros
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readdatavalid : in std_logic;
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readdata_master : in xfloat32;
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qparams_r : in std_logic;
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qparams_e : out std_logic;
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--! Cola de resultados
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qresult_d : in vectorblock04;
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qresult_q : out vectorblock04;
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--! Registro de parámetros
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paraminput : out vectorblock06;
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--! Cadena de sincronización
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sync_chain_0 : out std_logic;
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--! señales de colas vacias
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qresult_e : out std_logic_vector(3 downto 0);
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--! Colas de resultados
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qresult_w : in std_logic_vector(3 downto 0);
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qresult_rdec : in std_logic_vector(3 downto 0)
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);
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end component;
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--! Bloque decodificacion DataPath Control.
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component dpc
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port (
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clk : in std_logic;
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rst : in std_logic;
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paraminput : in vectorblock06; --! Vectores A,B
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prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.
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add32blko : in vectorblock03; --! Salidas de los 3 sumadores.
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inv32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
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sqr32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
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d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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qresult_q : in vectorblock04; --! Salida de las colas de resultados
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qresult_sel : in std_logic_vector (1 downto 0); --! Direccion con el resultado de la
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qresult_rdec : out std_logic_vector (3 downto 0); --!Señales de escritura decodificadas
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qresult_w : out std_logic_vector (3 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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qresult_d : out vectorblock04; --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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dataread : in std_logic;
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prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out vectorblock06; --! Entrada de los 6 sumandos del bloque de 3 sumadores.
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dataout : out xfloat32
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);
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end component;
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
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port (
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clk : in std_logic;
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rst : in std_logic;
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sign : in std_logic;
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prd32blki : in vectorblock12;
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add32blki : in vectorblock06;
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add32blko : out vectorblock03;
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prd32blko : out vectorblock06;
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sq32o : out xfloat32;
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inv32o : out xfloat32
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);
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end component;
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--! Componentes Aritméticos
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component fadd32
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port (
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clk : in std_logic;
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dpc : in std_logic;
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a32 : in xfloat32;
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b32 : in xfloat32;
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c32 : out xfloat32
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);
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end component;
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component fmul32
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port (
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clk : in std_logic;
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a32 : in xfloat32;
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b32 : in xfloat32;
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p32 : out xfloat32
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);
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end component;
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--! Bloque de Raiz Cuadrada
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component sqrt32
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port (
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clk : in std_logic;
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rd32: in xfloat32;
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sq32: out xfloat32
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);
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end component;
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--! Bloque de Inversores.
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component invr32
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port (
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clk : in std_logic;
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dvd32 : in xfloat32;
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qout32 : out xfloat32
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);
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end component;
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--! Contadores para la máquina de estados.
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component customCounter
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port (
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clk : in std_logic;
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rst : in std_logic;
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stateTrans : in std_logic;
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waitrequest_n : in std_logic;
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endaddress : in std_logic_vector (31 downto 2); --! Los 5 bits de arriba.
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startaddress : in std_logic_vector(31 downto 0);
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endaddressfetch : out std_logic;
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address_master : out std_logic_vector (31 downto 0)
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);
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end component;
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--! LPM_MULTIPLIER
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component lpm_mult
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generic (
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lpm_hint : string;
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lpm_pipeline : natural;
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lpm_representation : string;
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lpm_type : string;
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lpm_widtha : natural;
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lpm_widthb : natural;
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lpm_widthp : natural
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);
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port (
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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result : out std_logic_vector( lpm_widthp-1 downto 0 )
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);
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end component;
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--! LPM Memory Compiler.
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-- component scfifo
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-- generic (
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-- add_ram_output_register :string;
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-- allow_rwcycle_when_full :string;
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-- intended_device_family :string;
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-- lpm_hint :string;
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-- lpm_numwords :natural;
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-- lpm_showahead :string;
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-- lpm_type :string;
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-- lpm_width :natural;
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-- overflow_checking :string;
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-- underflow_checking :string;
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-- use_eab :string
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-- );
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-- port(
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-- rdreq : in std_logic;
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-- aclr : in std_logic;
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-- empty : out std_logic;
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-- clock : in std_logic;
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-- q : out std_logic_vector(lpm_width-1 downto 0);
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-- wrreq : in std_logic;
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-- data : in std_logic_vector(lpm_width-1 downto 0);
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-- almost_full : out std_logic;
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-- full : out std_logic
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-- );
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-- end component;
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type apCamera is record
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type apCamera is record
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resx,resy : integer;
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resx,resy : integer;
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width,height : real;
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width,height : real;
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