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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- memblock.vhd
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-- Rytrac.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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| Line 22... |
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.arithpack.all;
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entity raytrac is
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entity raytrac is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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| Line 45... |
Line 46... |
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--! Interrupciones
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--! Interrupciones
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int : out std_logic_vector (7 downto 0);
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int : out std_logic_vector (7 downto 0);
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--! Salidas
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--! Salidas
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q : out std_logic_vector (31 downto 0)
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q : out std_logic_vector (31 downto 0);
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--! Estado Controlador de Interrupciones
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intCtrlState : out iCtrlState;
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--! Estado Maquina de Estados
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smState : out macState
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);
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);
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end entity;
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end entity;
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architecture raytrac_arch of raytrac is
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architecture raytrac_arch of raytrac is
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--! Definicion de Tipos y de Constantes
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--! Señales de State Machine -> Memblock
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constant rstMasterValue : std_logic := '0';
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--!TBXSTART:SM
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signal s_adda : std_logic_vector (8 downto 0);
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--! Definición de componentes del sistema.
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signal s_addb : std_logic_vector (8 downto 0);
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signal s_iq_rd_ack : std_logic;
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--! Bloque de memorias
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--! Señales de State Machine -> DataPathControl
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component memblock
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signal s_sync_chain_0 : std_logic;
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generic (
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signal s_dpc_uca : std_logic_vector(2 downto 0);
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width : integer;
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signal s_eoi : std_logic;
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blocksize : integer;
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--! Señales de State Machine -> Testbench
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widthadmemblock : integer;
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signal s_smState : macState;
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external_writeable_blocks : integer;
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--!TBXEND
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external_readable_blocks : integer;
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--!TBXSTART:MBLK
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external_readable_widthad : integer;
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external_writeable_widthad : integer
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);
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port (
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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instrfifo_rd : in std_logic;
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resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
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instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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);
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end component;
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--! Bloque decodificacion DataPath Control.
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component dpc
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generic (
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width : integer
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);
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port (
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clk,rst : in std_logic;
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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eoi_int : in std_logic; --! Sennal de interrupción de final de instrucción.
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eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrupción de final de instrucción pero esta vez va asociada a la instruccón UCA.
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sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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fifo32x09_w : out std_logic;
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fifo32x23_w,fifo32x09_r : out std_logic;
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fifo32x23_r : out std_logic;
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resf_vector : in std_logic_vector(3 downto 0); --! Entradas de la señal de full de las colas de resultados.
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resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operación que está en curso.
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resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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end component;
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
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port (
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clk : in std_logic;
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rst : in std_logic;
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dpc : in std_logic;
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f : in std_logic_vector (12*32-1 downto 0);
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a : in std_logic_vector (8*32-1 downto 0);
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s : out std_logic_vector (4*32-1 downto 0);
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p : out std_logic_vector (6*32-1 downto 0)
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);
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end component;
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--! Bloque de Raiz Cuadrada
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component sqrt32
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port (
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clk : in std_logic;
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rd32: in std_logic_vector(31 downto 0);
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sq32: out std_logic_vector(31 downto 0)
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);
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end component;
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--! Bloque de Inversores.
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component invr32
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port (
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clk : in std_logic;
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dvd32 : in std_logic_vector(31 downto 0);
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qout32 : out std_logic_vector(31 downto 0)
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);
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end component;
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--! Maquina de Estados.
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component sm
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generic (
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width : integer ;
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widthadmemblock : integer
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--!external_readable_widthad :
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);
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port (
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--! Señales normales de secuencia.
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clk,rst: in std_logic;
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--! Vector con las instrucción codficada
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instrQq:in std_logic_vector(width-1 downto 0);
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--! Señal de cola vacia.
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instrQ_empty:in std_logic;
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adda,addb:out std_logic_vector (widthadmemblock-1 downto 0);
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sync_chain_0,instrRdAckd:out std_logic;
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full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
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--! End Of Instruction Event
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eoi : out std_logic;
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--! DataPath Control uca code.
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dpc_uca : out std_logic_vector (2 downto 0)
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);
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end component;
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--! Maquina de Interrupciones
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component im
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generic (
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num_events : integer ;
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cycles_to_wait : integer
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);
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port (
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clk,rst: in std_logic;
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rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
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eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
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eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
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rfull_int: out std_logic_vector(num_events-1downto 0) --! full results queue related interruptions
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);
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end component;
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--! Señales de Memblock -> State Machine
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--! Señales de Memblock -> State Machine
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signal s_iq_empty : std_logic;
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signal s_iq_empty : std_logic;
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signal s_iq : std_logic_vector (31 downto 0);
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signal s_iq : std_logic_vector (31 downto 0);
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--! Señales de Memblock -> Interruption Machine
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--! Señales de Memblock -> Interruption Machine
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signal s_rfull_events : std_logic_vector (3 downto 0); --Estas señales tambien entran a DPC.
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signal s_rfull_events : std_logic_vector (3 downto 0); --Estas señales tambien entran a DPC.
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--! Señales de Memblock -> DPC.
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--! Señales de Memblock -> DPC.
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signal s_q : std_logic_vector (12*32-1 downto 0);
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signal s_q : std_logic_vector (12*32-1 downto 0);
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signal s_normfifo_q : std_logic_vector (3*32-1 downto 0);
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signal s_normfifo_q : std_logic_vector (3*32-1 downto 0);
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signal s_dpfifo_q : std_logic_vector (2*32-1 downto 0);
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signal s_dpfifo_q : std_logic_vector (2*32-1 downto 0);
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--!TBXEND
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--! Señales de State Machine -> Memblock
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--!TBXSTART:SQR32
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signal s_adda : std_logic_vector (8 downto 0);
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--!Señales de Bloque de Raíz Cuadrada a DPC
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signal s_addb : std_logic_vector (8 downto 0);
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signal s_sq32 : std_logic_vector (31 downto 0);
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signal s_iq_rd_ack : std_logic;
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--!TBXEND
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--!TBXSTART:INV32
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--!Señales del bloque inversor a DPC.
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--! Señales de State Machine -> DataPathControl
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signal s_qout32 : std_logic_vector (31 downto 0);
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signal s_sync_chain_0 : std_logic;
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--!TBXEND
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signal s_dpc_uca : std_logic_vector(2 downto 0);
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--!TBXSTART:DPC
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signal s_eoi : std_logic;
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--! Señales de DataPathControl -> State Machine
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--! Señales de DataPathControl -> State Machine
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signal s_full_r : std_logic;
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signal s_full_r : std_logic;
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--! Señales de State Machin a Interruption Machine.
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signal s_eoi_events : std_logic_vector (3 downto 0);
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--! Señales de DPC a ArithBlock
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signal s_f : std_logic_vector (12*32-1 downto 0);
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signal s_a : std_logic_vector (8*32-1 downto 0);
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--! Parcialmente las señales de salida de los sumadores van al data path control.
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signal s_s : std_logic_vector (4*32-1 downto 0);
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signal s_p : std_logic_vector (6*32-1 downto 0);
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--! Señales de DPC a sqrt32.
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--! Señales de DPC a sqrt32.
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signal s_rd32 : std_logic_vector (31 downto 0);
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signal s_rd32 : std_logic_vector (31 downto 0);
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signal s_sq32 : std_logic_vector (31 downto 0);
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--! Señales de DPC a inv32.
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--! Señales de DPC a invr32.
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signal s_dvd32 : std_logic_vector (31 downto 0);
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signal s_dvd32 : std_logic_vector (31 downto 0);
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signal s_qout32 : std_logic_vector (31 downto 0);
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--! Señales de DPC a invr32.
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--! Señ que va desde DPC -> Memblock
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--! Señ que va desde DPC -> Memblock
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signal s_resultsfifo_w : std_logic_vector (4 downto 0);
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signal s_resultsfifo_w : std_logic_vector (4 downto 0);
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signal s_dpfifo_w : std_logic;
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signal s_dpfifo_w : std_logic;
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signal s_dpfifo_r : std_logic;
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signal s_dpfifo_r : std_logic;
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signal s_dpfifo_d : std_logic_vector (2*32-1 downto 0);
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signal s_dpfifo_d : std_logic_vector (2*32-1 downto 0);
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signal s_normfifo_w : std_logic;
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signal s_normfifo_w : std_logic;
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signal s_normfifo_r : std_logic;
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signal s_normfifo_r : std_logic;
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signal s_results_d : std_logic_vector (8*32-1 downto 0);
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signal s_results_d : std_logic_vector (8*32-1 downto 0);
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signal s_normfifo_d : std_logic_vector (3*32-1 downto 0);
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signal s_normfifo_d : std_logic_vector (3*32-1 downto 0);
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--!Señales de DPC a Interruption Machine
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signal s_eoi_events : std_logic_vector (3 downto 0);
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--! Señales de DPC a ArithBlock
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signal s_f : std_logic_vector (12*32-1 downto 0);
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signal s_a : std_logic_vector (8*32-1 downto 0);
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--! Parcialmente las señales de salida de los sumadores van al data path control.
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signal s_s : std_logic_vector (4*32-1 downto 0);
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signal s_p : std_logic_vector (6*32-1 downto 0);
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--!TBXEND
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--!TBXSTART:IM
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--! Señales de Interruption Machine al testbench
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signal s_iCtrlState : iCtrlState;
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--!TBXEND
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begin
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begin
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--! Instanciar el bloque de memorias MEMBLOCK
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--! Instanciar el bloque de memorias MEMBLOCK
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MemoryBlock : memblock
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MemoryBlock : memblock
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generic map (
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generic map (
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width => 32,
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width => 32,
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blocksize => 512,
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blocksize => 512,
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| Line 347... |
Line 211... |
clk => clk,
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clk => clk,
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dvd32 => s_dvd32,
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dvd32 => s_dvd32,
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qout32 => s_qout32
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qout32 => s_qout32
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);
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);
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--! Instanciar el bloque de raíz cuadrada.
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--! Instanciar el bloque de raíz cuadrada.
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square_root : sqrt32
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square_root : sqrt32
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port map (
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port map (
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clk => clk,
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clk => clk,
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rd32 => s_rd32,
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rd32 => s_rd32,
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sq32 => s_sq32
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sq32 => s_sq32
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);
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);
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--! Instanciar el bloque aritmético.
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--! Instanciar el bloque aritmético.
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arithmetic_block : arithblock
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arithmetic_block : arithblock
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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dpc => s_dpc_uca(1),
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dpc => s_dpc_uca(1),
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| Line 380... |
Line 244... |
clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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rfull_events => s_rfull_events,
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rfull_events => s_rfull_events,
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eoi_events => s_eoi_events,
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eoi_events => s_eoi_events,
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eoi_int => int(3 downto 0),
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eoi_int => int(3 downto 0),
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rfull_int => int(7 downto 4)
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rfull_int => int(7 downto 4),
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state => s_iCtrlState
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);
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);
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--!Instanciar la maquina de estados
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--!Instanciar la maquina de estados
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state_machine : sm
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state_machine : sm
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generic map (
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generic map (
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| Line 400... |
Line 265... |
addb => s_addb,
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addb => s_addb,
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sync_chain_0 => s_sync_chain_0,
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sync_chain_0 => s_sync_chain_0,
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instrRdAckd => s_iq_rd_ack,
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instrRdAckd => s_iq_rd_ack,
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full_r => s_full_r,
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full_r => s_full_r,
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eoi => s_eoi,
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eoi => s_eoi,
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dpc_uca => s_dpc_uca
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dpc_uca => s_dpc_uca,
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state => s_smState
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);
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);
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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