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--! @file raytrac.vhd
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--! @brief Sistema de Procesamiento Vectorial. La interface es compatible con el bus Avalon de Altera.
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- raytrac.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.arithpack.all;
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library altera_mf;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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use altera_mf.altera_mf_components.all;
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library lpm;
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library lpm;
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entity raytrac is
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entity raytrac is
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generic (
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generic (
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wd : integer := 32;
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wd : integer := 32;
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sl : integer := 5; --! Arith Sync Chain Long 2**sl
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ln : integer := 12; --! Max Transfer Length = 2**ln = n_outputbuffers * 256
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fd : integer := 8; --! Result Fifo Depth = 2**fd =256
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fd : integer := 8; --! Result Fifo Depth = 2**fd =256
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mb : integer := 4; --! Max Burst Length = 2**mb
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mb : integer := 4 --! Max Burst Length = 2**mb
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nr : integer := 4 --! Number of Registers = 2**nr
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);
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);
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
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--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
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attribute altera_attribute : string;
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attribute altera_attribute : string;
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attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
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attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
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subtype xfloat32 is std_logic_vector(wd-1 downto 0);
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type registerblock is array (15 downto 0) of xfloat32;
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type registerblock is array ((2**nr)-1 downto 0) of xfloat32;
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type transferState is (IDLE,SINK,SOURCE);
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type transferState is (IDLE,SINK,SOURCE);
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type upload_chain is (UPVX,UPVY,UPVZ,SC,DMA);
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constant rstMasterValue : std_logic :='0';
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type download_chain is (DWAX,DWAY,DWAZ,DWBX,DWBY,DWBZ,DWAXBX,DWAYBY,DWAZBZ);
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constant reg_ctrl : integer:=00;
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constant reg_ctrl : integer:=00;
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constant reg_vz : integer:=01;
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constant reg_vz : integer:=01;
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constant reg_vy : integer:=02;
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constant reg_vy : integer:=02;
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constant reg_vx : integer:=03;
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constant reg_vx : integer:=03;
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Line 130... |
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--! Avalon MM Slave
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--! Avalon MM Slave
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signal sreg_block : registerblock;
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signal sreg_block : registerblock;
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signal sslave_read : std_logic;
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signal sslave_read : std_logic;
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signal sslave_write : std_logic;
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signal sslave_write : std_logic;
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signal sslave_writedata : xfloat32;
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signal sslave_writedata : std_logic_vector (wd-1 downto 0);
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signal sslave_address : std_logic_vector (nr-1 downto 0);
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signal sslave_address : std_logic_vector (3 downto 0);
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signal sslave_waitrequest : std_logic;
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signal sslave_waitrequest : std_logic;
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--! Avalon MM Master
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--! Avalon MM Master
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signal smaster_write : std_logic;
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signal smaster_write : std_logic;
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signal smaster_read : std_logic;
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signal smaster_read : std_logic;
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signal sres_ack : std_logic;
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signal sres_ack : std_logic;
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signal soutb_ack : std_logic;
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signal soutb_ack : std_logic;
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signal sres_q : std_logic_vector(4*wd-1 downto 0);
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signal sres_q : std_logic_vector(4*wd-1 downto 0);
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signal sres_d : std_logic_vector(4*wd-1 downto 0);
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signal sres_d : vectorblock04;
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signal soutb_d : std_logic_vector(wd-1 downto 0);
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signal soutb_d : std_logic_vector(wd-1 downto 0);
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signal sres_w : std_logic;
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signal sres_w : std_logic;
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signal soutb_w : std_logic;
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signal soutb_w : std_logic;
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Line 172... |
signal sparamload_pending : std_logic;
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signal sparamload_pending : std_logic;
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signal sZeroTransit : std_logic;
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signal sZeroTransit : std_logic;
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--!Unload Control
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--!Unload Control
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type upload_chain is (VX,VY,VZ,SC,DMA);
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signal supload_chain : upload_chain;
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signal supload_chain : upload_chain;
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signal supload_start : upload_chain;
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signal supload_start : upload_chain;
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--!Señales de apoyo:
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--!Señales de apoyo:
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signal zero : std_logic_vector(31 downto 0);
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signal zero : std_logic_vector(31 downto 0);
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--!High Register Bank Control Signals or AKA Load Sync Chain Control
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--!High Register Bank Control Signals or AKA Load Sync Chain Control
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type download_chain is (AX,AY,AZ,BX,BY,BZ,AXBX,AYBY,AZBZ);
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signal sdownload_chain : download_chain;
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signal sdownload_chain : download_chain;
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signal sdownload_start : download_chain;
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signal sdownload_start : download_chain;
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signal srestart_chain : std_logic;
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signal srestart_chain : std_logic;
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--!State Machine Hysteresis Control Signals
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--!State Machine Hysteresis Control Signals
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signal sdrain_condition : std_logic;
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signal sdrain_condition : std_logic;
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sflood_condition : std_logic;
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signal sflood_condition : std_logic;
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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--! Arithmetic Pipeline and Data Path Control
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component ap_n_dpc
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port (
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clk : in std_logic;
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rst : in std_logic;
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begin
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paraminput : in vectorblock06; --! Vectores A,B
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--! Unos y ceros
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d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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zero <= (others => '0');
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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sync_chain_pending : out std_logic;
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--! Salidas no asignadas
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qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
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qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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end component;
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--! Mientras tanto
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signal sparaminput : vectorblock06;
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ssync_chain_pending <= ssync_chain_1;
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sres_d ((wd*1)-1 downto wd*0)<= sreg_block(reg_bz) ;
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sres_d ((wd*2)-1 downto wd*1)<= sreg_block(reg_by) ;
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sres_d ((wd*3)-1 downto wd*2)<= sreg_block(reg_bx) ;
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sres_d ((wd*4)-1 downto wd*3)<= sreg_block(reg_ax) ;
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sres_w <= ssync_chain_1;
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begin
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--!Zero agreggate
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zero <= (others => '0');
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sparaminput(ax) <= sreg_block(reg_ax);
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sparaminput(ay) <= sreg_block(reg_ay);
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sparaminput(az) <= sreg_block(reg_az);
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sparaminput(bx) <= sreg_block(reg_bx);
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sparaminput(by) <= sreg_block(reg_by);
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sparaminput(bz) <= sreg_block(reg_bz);
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! AVALON MEMORY MAPPED MASTER INTERFACE BEGIN => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
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--! ARITHMETIC PIPELINE AND DATA PATH INSTANTIATION => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! Arithpipeline and Datapath Control Instance
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arithmetic_pipeline_and_datapath_controller : ap_n_dpc
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port map (
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clk => clk,
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rst => rst,
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paraminput => sparaminput,
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d => sreg_block(reg_ctrl)(reg_ctrl_d),
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c => sreg_block(reg_ctrl)(reg_ctrl_c),
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s => sreg_block(reg_ctrl)(reg_ctrl_s),
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sync_chain_1 => ssync_chain_1,
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sync_chain_pending => ssync_chain_pending,
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qresult_w => sres_w,
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qresult_d => sres_d
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);
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! TRANSFER CONTROL RTL CODE
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--! TRANSFER CONTROL RTL CODE
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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TRANSFER_CONTROL:
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TRANSFER_CONTROL:
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process(clk,rst,master_waitrequest,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,sres_e,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
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process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,sres_e,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
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begin
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begin
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--! Conexióln a señales externas.
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--! Conexióln a señales externas.
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irq <= sreg_block(reg_ctrl)(reg_ctrl_irq);
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irq <= sreg_block(reg_ctrl)(reg_ctrl_irq);
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master_read <= smaster_read;
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master_read <= smaster_read;
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Line 290... |
else
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else
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sload_add_pending <= '1';
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sload_add_pending <= '1';
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end if;
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end if;
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--! ELEMENTO DE SINCRONIZACION CARGA DE OPERANDOS: Se están cargando los operandos que serán operados en el pipeline aritmético.
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--! ELEMENTO DE SINCRONIZACION CARGA DE OPERANDOS: Se están cargando los operandos que serán operados en el pipeline aritmético.
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if sdownload_chain /= AX and sdownload_chain /= AXBX then
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if sdownload_chain /= DWAX and sdownload_chain /= DWAXBX then
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sparamload_pending <= '1';
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sparamload_pending <= '1';
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else
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else
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sparamload_pending <= '0';
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sparamload_pending <= '0';
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end if;
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end if;
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--! Flow Control: Existe un número de descargas programadas por el sistema, comenzar a realizarlas.
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--! Flow Control: Existe un número de descargas programadas por el sistema, comenzar a realizarlas.
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--! Ir al estado Source.
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--! Ir al estado Source.
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sm <= SOURCE;
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sm <= SOURCE;
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '1';
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '1';
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else
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
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end if;
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end if;
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end if;
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end if;
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when others =>
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null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! FLOW CONTROL RTL CODE
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--! FLOW CONTROL RTL CODE
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! Colas de resultados y buffer de salida
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--! Colas de resultados y buffer de salida
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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res:scfifo
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res:scfifo
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generic map (lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 128, lpm_widthu => fd, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
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generic map (lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 128, lpm_widthu => fd, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
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port map (rdreq => sres_ack, aclr => '0', empty => sres_e, clock => clk, q => sres_q, wrreq => sres_w, data => sres_d);
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port map (rdreq => sres_ack, aclr => '0', empty => sres_e, clock => clk, q => sres_q, wrreq => sres_w, data => sres_d(qsc)&sres_d(qx)&sres_d(qy)&sres_d(qz));
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output_buffer:scfifo
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output_buffer:scfifo
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generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
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generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
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port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
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port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! PROCESO DE CONTROL DE FLUJO ENTRE EL BUFFER DE RESULTADOS Y EL BUFFER DE SALIDA
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--! PROCESO DE CONTROL DE FLUJO ENTRE EL BUFFER DE RESULTADOS Y EL BUFFER DE SALIDA
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Line 540... |
end if;
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end if;
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--! Control de lectura de la cola de resultados.
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--! Control de lectura de la cola de resultados.
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if sres_e='0' then
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if sres_e='0' then
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--!Hay datos en la cola de resultados.
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--!Hay datos en la cola de resultados.
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if (supload_chain=VZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
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if (supload_chain=UPVZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
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--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
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--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
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sres_ack <= '1';
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sres_ack <= '1';
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else
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sres_ack <= '0';
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end if;
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end if;
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else
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else
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sres_ack <= '0';
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sres_ack <= '0';
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end if;
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end if;
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--! Decodificar que salida de la cola de resultados se conecta a la entrada del otput buffer
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--! Decodificar que salida de la cola de resultados se conecta a la entrada del otput buffer
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--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexión
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--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexión
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case supload_chain is
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case supload_chain is
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when VX =>
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when UPVX =>
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soutb_d <= sres_q ((wd*1)-1 downto wd*0);
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soutb_d <= sres_q (32*qx+31 downto 32*qx);
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when VY =>
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when UPVY =>
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soutb_d <= sres_q ((wd*2)-1 downto wd*1);
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soutb_d <= sres_q (32*qy+31 downto 32*qy);
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when VZ =>
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when UPVZ =>
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soutb_d <= sres_q ((wd*3)-1 downto wd*2);
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soutb_d <= sres_q (32*qz+31 downto 32*qz);
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when SC =>
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when SC =>
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soutb_d <= sres_q ((wd*4)-1 downto wd*3);
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soutb_d <= sres_q (32*qsc+31 downto 32*qsc);
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when DMA =>
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when DMA =>
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soutb_d <= master_readdata;
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soutb_d <= master_readdata;
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end case;
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end case;
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case sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc) is
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case sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc) is
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when "01" =>
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when "01" =>
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supload_start <= SC;
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supload_start <= SC;
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when others =>
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when others =>
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supload_start <= VX;
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supload_start <= UPVX;
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end case;
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end case;
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--! Máquina de estados para el width adaptation RES(128) -> OUTPUTBUFFER(32).
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--! Máquina de estados para el width adaptation RES(128) -> OUTPUTBUFFER(32).
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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supload_chain <= VX;
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supload_chain <= UPVX;
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elsif clk'event and clk='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
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elsif clk'event and clk='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
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--! Modo de operación normal.
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--! Modo de operación normal.
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case supload_chain is
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case supload_chain is
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when VX =>
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when UPVX =>
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if sres_e='1' then
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if sres_e='1' then
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supload_chain <= supload_start;
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supload_chain <= supload_start;
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else
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else
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supload_chain <= VY;
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supload_chain <= UPVY;
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end if;
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end if;
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when VY =>
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when UPVY =>
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supload_chain <= VZ;
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supload_chain <= UPVZ;
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when VZ =>
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when UPVZ =>
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if sreg_block(reg_ctrl)(reg_ctrl_sc)='0' then
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if sreg_block(reg_ctrl)(reg_ctrl_sc)='0' then
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supload_chain <= VX;
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supload_chain <= UPVX;
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else
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else
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supload_chain <= SC;
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supload_chain <= SC;
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end if;
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end if;
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when SC|DMA =>
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when SC|DMA =>
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supload_chain <= supload_start;
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supload_chain <= supload_start;
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| Line 561... |
Line 614... |
--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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FLOW_CONTROL_INPUT_STAGE:
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FLOW_CONTROL_INPUT_STAGE:
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process(clk,rst,master_readdatavalid,master_readdata,sreg_block(reg_ctrl)(reg_ctrl_dma downto reg_ctrl_s),sslave_write,sslave_address,supload_chain)
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process(clk,rst,master_readdatavalid,master_readdata,sreg_block(reg_ctrl)(reg_ctrl_dma downto reg_ctrl_s),sslave_write,sslave_address,supload_chain)
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begin
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begin
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--! Está ocurriendo un evento de transición del estado TX al estado FETCH: Programar el enganche de parámetros que vienen de la interconexión.
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--! Está ocurriendo un evento de transición del estado TX al estado FETCH: Programar el enganche de parámetros que vienen de la interconexión.
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--! Mirar como es la carga inicial. Si es Normalizacion o Magnitud (dcs=110) entonces cargar AXBX de lo contrario solo AX.
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--! Mirar como es la carga inicial. Si es Normalizacion o Magnitud (dcs=110) entonces cargar DWAXBX de lo contrario solo DWAX.
|
case sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s) is
|
case sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s) is
|
when "110" | "100" => sdownload_start <= AXBX;
|
when "110" | "100" => sdownload_start <= DWAXBX;
|
when others => sdownload_start <= AX;
|
when others => sdownload_start <= DWAX;
|
end case;
|
end case;
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sdownload_chain <= AX;
|
sdownload_chain <= DWAX;
|
for i in reg_bz downto reg_ax loop
|
for i in reg_bz downto reg_ax loop
|
sreg_block(i) <= (others => '0');
|
sreg_block(i) <= (others => '0');
|
end loop;
|
end loop;
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
if master_readdatavalid='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
|
if master_readdatavalid='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
|
--! El dato en la interconexión es valido, se debe enganchar.
|
--! El dato en la interconexión es valido, se debe enganchar.
|
case sdownload_chain is
|
case sdownload_chain is
|
when AX | AXBX =>
|
when DWAX | DWAXBX =>
|
--! Cargar el operando correspondiente al componente "X" del vector "A"
|
--! Cargar el operando correspondiente al componente "X" del vector "A"
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sreg_block(reg_ax) <= master_readdata;
|
sreg_block(reg_ax) <= master_readdata;
|
if sdownload_start = AXBX then
|
if sdownload_start = DWAXBX then
|
--! Operación Unaria por ejemplo magnitud de un vector
|
--! Operación Unaria por ejemplo magnitud de un vector
|
--! Escribir en el registro bx adicionalmente.
|
--! Escribir en el registro bx adicionalmente.
|
sreg_block(reg_bx) <= master_readdata;
|
sreg_block(reg_bx) <= master_readdata;
|
--! El siguiente estado es cargar el componente "Y" de del operando a ejecutar.
|
--! El siguiente estado es cargar el componente "Y" de del operando a ejecutar.
|
sdownload_chain <= AYBY;
|
sdownload_chain <= DWAYBY;
|
else
|
else
|
--! Operación de dos operandos. Por ejemplo Producto Cruz.
|
--! Operación de dos operandos. Por ejemplo Producto Cruz.
|
--! El siguiente estado es cargar el vector "Y" del operando "A".
|
--! El siguiente estado es cargar el vector "Y" del operando "A".
|
sdownload_chain <= AY;
|
sdownload_chain <= DWAY;
|
end if;
|
end if;
|
when AY | AYBY =>
|
when DWAY | DWAYBY =>
|
sreg_block(reg_ay) <= master_readdata;
|
sreg_block(reg_ay) <= master_readdata;
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
if sdownload_chain = AYBY then
|
if sdownload_chain = DWAYBY then
|
sreg_block(reg_by) <= master_readdata;
|
sreg_block(reg_by) <= master_readdata;
|
sdownload_chain <= AZBZ;
|
sdownload_chain <= DWAZBZ;
|
else
|
else
|
sdownload_chain <= AZ;
|
sdownload_chain <= DWAZ;
|
end if;
|
end if;
|
when AZ | AZBZ =>
|
when DWAZ | DWAZBZ =>
|
sreg_block(reg_az) <= master_readdata;
|
sreg_block(reg_az) <= master_readdata;
|
if sdownload_chain=AZBZ then
|
if sdownload_chain=DWAZBZ then
|
ssync_chain_1 <= '1';
|
ssync_chain_1 <= '1';
|
sreg_block(reg_bz) <= master_readdata;
|
sreg_block(reg_bz) <= master_readdata;
|
sdownload_chain <= AXBX;
|
sdownload_chain <= DWAXBX;
|
else
|
else
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sdownload_chain <= BX;
|
sdownload_chain <= DWBX;
|
end if;
|
end if;
|
when BX =>
|
when DWBX =>
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sreg_block(reg_bx) <= master_readdata;
|
sreg_block(reg_bx) <= master_readdata;
|
sdownload_chain <= BY;
|
sdownload_chain <= DWBY;
|
when BY =>
|
when DWBY =>
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sreg_block(reg_by) <= master_readdata;
|
sreg_block(reg_by) <= master_readdata;
|
sdownload_chain <= BZ;
|
sdownload_chain <= DWBZ;
|
when BZ =>
|
when DWBZ =>
|
sreg_block(reg_bz) <= master_readdata;
|
sreg_block(reg_bz) <= master_readdata;
|
ssync_chain_1 <= '1';
|
ssync_chain_1 <= '1';
|
if sreg_block(reg_ctrl)(reg_ctrl_cmb)='1' then
|
if sreg_block(reg_ctrl)(reg_ctrl_cmb)='1' then
|
sdownload_chain <= BX;
|
sdownload_chain <= DWBX;
|
else
|
else
|
sdownload_chain <= AX;
|
sdownload_chain <= DWAX;
|
end if;
|
end if;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
| Line 798... |
Line 851... |
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Data Fetch Start Address (reg_fetchstart) BASE_ADDRESS + 0x20 |
|
--! Data Fetch Start Address (reg_fetchstart) BASE_ADDRESS + 0x20 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Data Write Start Address (reg_sinkstart) BASE_ADDRESS + 0x24 |
|
--! Data Write Start Address (reg_sinkstart) BASE_ADDRESS + 0x24 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter Ax component (reg_ax) BASE_ADDRESS + 0x28 |
|
--! Parameter AX component (reg_ax) BASE_ADDRESS + 0x28 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter Ay component (reg_ay) BASE_ADDRESS + 0x2C |
|
--! Parameter Ay component (reg_ay) BASE_ADDRESS + 0x2C |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter Az component (reg_az) BASE_ADDRESS + 0x30 |
|
--! Parameter Az component (reg_az) BASE_ADDRESS + 0x30 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
