| Line 88... |
Line 88... |
constant reg_ctrl : integer:=00;
|
constant reg_ctrl : integer:=00;
|
constant reg_vz : integer:=01;
|
constant reg_vz : integer:=01;
|
constant reg_vy : integer:=02;
|
constant reg_vy : integer:=02;
|
constant reg_vx : integer:=03;
|
constant reg_vx : integer:=03;
|
constant reg_scalar : integer:=04;
|
constant reg_scalar : integer:=04;
|
constant reg_scratch00 : integer:=05;
|
constant reg_nfetch : integer:=05;
|
constant reg_outputcounter : integer:=06;
|
constant reg_outputcounter : integer:=06;
|
constant reg_inputcounter : integer:=07;
|
constant reg_inputcounter : integer:=07;
|
constant reg_fetchstart : integer:=08;
|
constant reg_fetchstart : integer:=08;
|
constant reg_sinkstart : integer:=09;
|
constant reg_sinkstart : integer:=09;
|
constant reg_ax : integer:=10;
|
constant reg_ax : integer:=10;
|
| Line 125... |
Line 125... |
constant reg_ctrl_rom : integer:=15; --! ROM bit : Read Only Mode bit.
|
constant reg_ctrl_rom : integer:=15; --! ROM bit : Read Only Mode bit.
|
|
|
constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
|
constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
|
constant reg_ctrl_aeb : integer:=17; --! A==B.
|
constant reg_ctrl_aeb : integer:=17; --! A==B.
|
constant reg_ctrl_ageb : integer:=18; --! A>=B.
|
constant reg_ctrl_ageb : integer:=18; --! A>=B.
|
constant reg_ctrl_nfetch_low : integer:=19; --! NFETCH_LOW : Lower bit to program the number of addresses to load in the interconnection.
|
|
constant reg_ctrl_nfetch_high : integer:=30; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
|
|
constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
|
constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
|
|
|
|
--! Nfetch Reg Mask
|
|
constant reg_nfetch_high : integer:=11; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
|
|
|
|
|
--! Avalon MM Slave
|
--! Avalon MM Slave
|
|
|
signal sreg_block : registerblock;
|
signal sreg_block : registerblock;
|
signal sslave_read : std_logic;
|
signal sslave_read : std_logic;
|
| Line 187... |
Line 188... |
signal sdownload_start : download_chain;
|
signal sdownload_start : download_chain;
|
signal srestart_chain : std_logic;
|
signal srestart_chain : std_logic;
|
--!State Machine Hysteresis Control Signals
|
--!State Machine Hysteresis Control Signals
|
signal sdrain_condition : std_logic;
|
signal sdrain_condition : std_logic;
|
signal sdrain_burstcount : std_logic_vector(mb downto 0);
|
signal sdrain_burstcount : std_logic_vector(mb downto 0);
|
signal sdata_fetch_counter : std_logic_vector(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low);
|
signal sdata_fetch_counter : std_logic_vector(reg_nfetch_high downto 0);
|
signal sburstcount_sink : std_logic_vector(mb downto 0);
|
signal sburstcount_sink : std_logic_vector(mb downto 0);
|
|
|
signal sflood_condition : std_logic;
|
signal sflood_condition : std_logic;
|
signal sflood_burstcount : std_logic_vector(mb downto 0);
|
signal sflood_burstcount : std_logic_vector(mb downto 0);
|
|
|
| Line 276... |
Line 277... |
--! ELEMENTO DE SINCRONIZACION OUT QUEUE: Datos pendientes por cargar a la memoria a través de la interconexión
|
--! ELEMENTO DE SINCRONIZACION OUT QUEUE: Datos pendientes por cargar a la memoria a través de la interconexión
|
swrite_pending <= not(soutb_e);
|
swrite_pending <= not(soutb_e);
|
|
|
|
|
--! ELEMENTO DE SINCRONIZACION DESCARGA DE DATOS: Hay datos pendientes por descargar desde la memoria a través de la interconexión.
|
--! ELEMENTO DE SINCRONIZACION DESCARGA DE DATOS: Hay datos pendientes por descargar desde la memoria a través de la interconexión.
|
if sdata_fetch_counter=zero(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low) then
|
if sdata_fetch_counter=zero(reg_nfetch_high downto 0) then
|
sfetch_data_pending <= '0';
|
sfetch_data_pending <= '0';
|
else
|
else
|
sfetch_data_pending <= '1';
|
sfetch_data_pending <= '1';
|
end if;
|
end if;
|
|
|
--! ELEMENTO DE SINCRONIZACION CARGA DE DIRECCIONES: Hay direcciones pendientes por cargar a la interconexión?
|
--! ELEMENTO DE SINCRONIZACION CARGA DE DIRECCIONES: Hay direcciones pendientes por cargar a la interconexión?
|
if sreg_block(reg_ctrl)(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low)=zero(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low) then
|
if sreg_block(reg_nfetch)(reg_nfetch_high downto 0)=zero(reg_nfetch_high downto 0) then
|
sload_add_pending <= '0';
|
sload_add_pending <= '0';
|
else
|
else
|
sload_add_pending <= '1';
|
sload_add_pending <= '1';
|
end if;
|
end if;
|
|
|
| Line 304... |
Line 305... |
sflood_condition <= '1';
|
sflood_condition <= '1';
|
else
|
else
|
--! Flow Control : La saturación de la cola de resultados debe parar porque está casí llena.
|
--! Flow Control : La saturación de la cola de resultados debe parar porque está casí llena.
|
sflood_condition <= '0';
|
sflood_condition <= '0';
|
end if;
|
end if;
|
if sreg_block(reg_ctrl)(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low+mb)/=zero(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low+mb) then
|
if sreg_block(reg_nfetch)(reg_nfetch_high downto 0+mb)/=zero(reg_nfetch_high downto 0+mb) then
|
--! Flow Control: Si el número de descargas pendientes es mayor o igual al max burst length, entonces cargar max burst en el contador.
|
--! Flow Control: Si el número de descargas pendientes es mayor o igual al max burst length, entonces cargar max burst en el contador.
|
sflood_burstcount <= '1'&zero(mb-1 downto 0);
|
sflood_burstcount <= '1'&zero(mb-1 downto 0);
|
else
|
else
|
--! Flow Control: Si le número de descargas pendientes es inferior a Max Burst Count entonces cargar los bits menos significativos del registro de descargas pendientes.
|
--! Flow Control: Si le número de descargas pendientes es inferior a Max Burst Count entonces cargar los bits menos significativos del registro de descargas pendientes.
|
sflood_burstcount <= '0'&sreg_block(reg_ctrl)(reg_ctrl_nfetch_low+mb-1 downto reg_ctrl_nfetch_low);
|
sflood_burstcount <= '0'&sreg_block(reg_ctrl)(0+mb-1 downto 0);
|
end if;
|
end if;
|
|
|
--! Se debe iniciar una transacción de carga de datos hacia la memoria externa?
|
--! Se debe iniciar una transacción de carga de datos hacia la memoria externa?
|
if soutb_ae='1' then
|
if soutb_ae='1' then
|
--! Flow Control : Cuando se esté drenando la cola de resultados, si la cola está casí vac&iaute;a, la longitud del burst serán los bits menos significativos del contador de la cola.
|
--! Flow Control : Cuando se esté drenando la cola de resultados, si la cola está casí vac&iaute;a, la longitud del burst serán los bits menos significativos del contador de la cola.
|
| Line 366... |
Line 367... |
--! Control and Status Register
|
--! Control and Status Register
|
sreg_block(reg_ctrl) <= (others => '0');
|
sreg_block(reg_ctrl) <= (others => '0');
|
--! Contador Overall
|
--! Contador Overall
|
sreg_block(reg_inputcounter) <= (others => '0');
|
sreg_block(reg_inputcounter) <= (others => '0');
|
sreg_block(reg_outputcounter) <= (others => '0');
|
sreg_block(reg_outputcounter) <= (others => '0');
|
|
--! Address Fetch Counter
|
|
sreg_block(reg_nfetch) <= (others => '0');
|
|
|
|
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
|
|
--! Nevermind the State, discount the incoming valid data counter.
|
--! Nevermind the State, discount the incoming valid data counter.
|
| Line 394... |
Line 397... |
master_address <= sreg_block(reg_fetchstart);
|
master_address <= sreg_block(reg_fetchstart);
|
master_burstcount <= sflood_burstcount;
|
master_burstcount <= sflood_burstcount;
|
sdata_fetch_counter <= sdata_fetch_counter+sflood_burstcount-master_readdatavalid;
|
sdata_fetch_counter <= sdata_fetch_counter+sflood_burstcount-master_readdatavalid;
|
--! Context Saving:
|
--! Context Saving:
|
sreg_block(reg_fetchstart) <= sreg_block(reg_fetchstart) + (sflood_burstcount&"00");
|
sreg_block(reg_fetchstart) <= sreg_block(reg_fetchstart) + (sflood_burstcount&"00");
|
sreg_block(reg_ctrl)(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low) <= sreg_block(reg_ctrl)(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low) - sflood_burstcount;
|
sreg_block(reg_nfetch)(reg_nfetch_high downto 0) <= sreg_block(reg_nfetch)(reg_nfetch_high downto 0) - sflood_burstcount;
|
else
|
else
|
--! Flow Control : Cambiar al estado SINK, porque o está muy llena la cola de salida o no hay descargas pendientes por realizar.
|
--! Flow Control : Cambiar al estado SINK, porque o está muy llena la cola de salida o no hay descargas pendientes por realizar.
|
sm <= SINK;
|
sm <= SINK;
|
end if;
|
end if;
|
else --master_read=1;
|
else --master_read=1;
|
| Line 479... |
Line 482... |
if sslave_write='1' then
|
if sslave_write='1' then
|
case sslave_address is
|
case sslave_address is
|
when x"0" =>
|
when x"0" =>
|
--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
|
--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
|
if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
|
if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
|
sreg_block(reg_ctrl)(reg_ctrl_irq downto reg_ctrl_nfetch_low) <= sslave_writedata(reg_ctrl_irq downto reg_ctrl_nfetch_low);
|
sreg_block(reg_ctrl)(reg_ctrl_irq downto 0) <= sslave_writedata(reg_ctrl_irq downto 0);
|
sreg_block(reg_ctrl)(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb) <= sslave_writedata(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb);
|
sreg_block(reg_ctrl)(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb) <= sslave_writedata(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb);
|
sreg_block(reg_ctrl)(reg_ctrl_rlsc) <= sslave_writedata(reg_ctrl_rlsc);
|
sreg_block(reg_ctrl)(reg_ctrl_rlsc) <= sslave_writedata(reg_ctrl_rlsc);
|
sreg_block(reg_ctrl)(reg_ctrl_ageb downto reg_ctrl_alb) <=sslave_writedata(reg_ctrl_ageb downto reg_ctrl_alb);
|
sreg_block(reg_ctrl)(reg_ctrl_ageb downto reg_ctrl_alb) <=sslave_writedata(reg_ctrl_ageb downto reg_ctrl_alb);
|
end if;
|
end if;
|
|
when x"5" => sreg_block(reg_nfetch) <= sslave_writedata;
|
when x"6" => sreg_block(reg_outputcounter) <= sslave_writedata;
|
when x"6" => sreg_block(reg_outputcounter) <= sslave_writedata;
|
when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
|
when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
|
when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
|
when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
|
when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
|
when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
|
when others => null;
|
when others => null;
|
| Line 701... |
Line 705... |
--! Master Slave Process: Proceso para la escritura y lectura de registros desde el NIOS II.
|
--! Master Slave Process: Proceso para la escritura y lectura de registros desde el NIOS II.
|
low_register_bank:
|
low_register_bank:
|
process (clk,rst,sreg_block,soutb_w,supload_chain)
|
process (clk,rst,sreg_block,soutb_w,supload_chain)
|
begin
|
begin
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
for i in reg_scratch00 downto reg_vz loop
|
for i in reg_scalar downto reg_vz loop
|
sreg_block(i) <= (others => '0');
|
sreg_block(i) <= (others => '0');
|
end loop;
|
end loop;
|
|
|
slave_readdata <= (others => '0');
|
slave_readdata <= (others => '0');
|
sslave_address <= (others => '0');
|
sslave_address <= (others => '0');
|
| Line 719... |
Line 723... |
sslave_write <= slave_write;
|
sslave_write <= slave_write;
|
sslave_read <= slave_read;
|
sslave_read <= slave_read;
|
sslave_writedata <= slave_writedata;
|
sslave_writedata <= slave_writedata;
|
|
|
|
|
for i in reg_scratch00 downto reg_vz loop
|
for i in reg_scalar downto reg_vz loop
|
if sslave_address=i then
|
if sslave_address=i then
|
if sslave_write='1' then
|
if sslave_write='1' then
|
sreg_block(i) <= sslave_writedata;
|
sreg_block(i) <= sslave_writedata;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 842... |
Line 846... |
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Result Vector X component (reg_vx) BASE_ADDRESS + 0xC |
|
--! Result Vector X component (reg_vx) BASE_ADDRESS + 0xC |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Result Vector Scalar component (reg_scalar) BASE_ADDRESS + 0x10 |
|
--! Result Vector Scalar component (reg_scalar) BASE_ADDRESS + 0x10 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Scratch Vector 00 (reg_scratch00) BASE_ADDRESS + 0x14 |
|
--! Scratch Vector 00 (reg_nfetch) BASE_ADDRESS + 0x14 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! output Data Counter (reg_outputcounter) BASE_ADDRESS + 0x18 |
|
--! output Data Counter (reg_outputcounter) BASE_ADDRESS + 0x18 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Input Data Counter (reg_inputcounter) BASE_ADDRESS + 0x1C |
|
--! Input Data Counter (reg_inputcounter) BASE_ADDRESS + 0x1C |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
