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[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac.vhd] - Diff between revs 237 and 243

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Rev 237 Rev 243
Line 194... Line 194...
        signal sburstcount_sink         : std_logic_vector(mb downto 0);
        signal sburstcount_sink         : std_logic_vector(mb downto 0);
 
 
        signal sflood_condition         : std_logic;
        signal sflood_condition         : std_logic;
        signal sflood_burstcount        : std_logic_vector(mb downto 0);
        signal sflood_burstcount        : std_logic_vector(mb downto 0);
 
 
 
        signal sp0,sp1,sp2                      : std_logic_vector(31 downto 0);
        --! Arithmetic Pipeline and Data Path Control
        --! Arithmetic Pipeline and Data Path Control
        component ap_n_dpc
        component ap_n_dpc
        port (
        port (
 
 
 
                p0,p1,p2                                        : out std_logic_vector(31 downto 0);
                clk                                             : in    std_logic;
                clk                                             : in    std_logic;
                rst                                             : in    std_logic;
                rst                                             : in    std_logic;
                ax                                              : in    std_logic_vector(31 downto 0);
                ax                                              : in    std_logic_vector(31 downto 0);
                ay                                              : in    std_logic_vector(31 downto 0);
                ay                                              : in    std_logic_vector(31 downto 0);
                az                                              : in    std_logic_vector(31 downto 0);
                az                                              : in    std_logic_vector(31 downto 0);
Line 233... Line 236...
--! *************************************************************************************************************************************************************************************************************************************************************
--! *************************************************************************************************************************************************************************************************************************************************************
 
 
        --! Arithpipeline and Datapath Control Instance
        --! Arithpipeline and Datapath Control Instance
        arithmetic_pipeline_and_datapath_controller : ap_n_dpc
        arithmetic_pipeline_and_datapath_controller : ap_n_dpc
        port map (
        port map (
 
                p0                              => sp0,
 
                p1                              => sp1,
 
                p2                              => sp2,
                clk                             => clk,
                clk                             => clk,
                rst                             => rst,
                rst                             => rst,
                ax                                      => sreg_block(reg_ax),
                ax                                      => sreg_block(reg_ax),
                ay                                      => sreg_block(reg_ay),
                ay                                      => sreg_block(reg_ay),
                az                                      => sreg_block(reg_az),
                az                                      => sreg_block(reg_az),
Line 721... Line 727...
                        sslave_address          <= slave_address;
                        sslave_address          <= slave_address;
                        sslave_write            <= slave_write;
                        sslave_write            <= slave_write;
                        sslave_read                     <= slave_read;
                        sslave_read                     <= slave_read;
                        sslave_writedata        <= slave_writedata;
                        sslave_writedata        <= slave_writedata;
 
 
 
                        sreg_block(reg_vz) <= sp0;
                        for i in reg_scalar downto reg_vz loop
                        sreg_block(reg_vy) <= sp1;
 
                        sreg_block(reg_vx) <= sp2;
 
                        for i in reg_scalar downto reg_scalar loop
                                if sslave_address=i then
                                if sslave_address=i then
                                        if sslave_write='1' then
                                        if sslave_write='1' then
                                                sreg_block(i) <= sslave_writedata;
                                                sreg_block(i) <= sslave_writedata;
                                        end if;
                                        end if;
                                end if;
                                end if;
Line 738... Line 746...
                                        end if;
                                        end if;
                                end if;
                                end if;
                        end loop;
                        end loop;
                end if;
                end if;
        end process;
        end process;
 
 
--! *************************************************************************************************************************************************************************************************************************************************************
--! *************************************************************************************************************************************************************************************************************************************************************
--! AVALON MEMORY MAPPED SLAVE FINISHED
--! AVALON MEMORY MAPPED SLAVE FINISHED
--! *************************************************************************************************************************************************************************************************************************************************************
--! *************************************************************************************************************************************************************************************************************************************************************
        --!---------|-----------|-------------------------------------------------------------------------------------------------------------------
        --!---------|-----------|-------------------------------------------------------------------------------------------------------------------
        --! Control Register (reg_ctrl) BASE_ADDRESS + 0x0                                                                                                                                                                                              |
        --! Control Register (reg_ctrl) BASE_ADDRESS + 0x0                                                                                                                                                                                              |

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