| Line 194... |
Line 194... |
signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sflood_condition : std_logic;
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signal sflood_condition : std_logic;
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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signal sp0,sp1,sp2 : std_logic_vector(31 downto 0);
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--! Arithmetic Pipeline and Data Path Control
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--! Arithmetic Pipeline and Data Path Control
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component ap_n_dpc
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component ap_n_dpc
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port (
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port (
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p0,p1,p2 : out std_logic_vector(31 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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ax : in std_logic_vector(31 downto 0);
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ax : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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| Line 233... |
Line 236... |
--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! Arithpipeline and Datapath Control Instance
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--! Arithpipeline and Datapath Control Instance
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arithmetic_pipeline_and_datapath_controller : ap_n_dpc
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arithmetic_pipeline_and_datapath_controller : ap_n_dpc
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port map (
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port map (
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p0 => sp0,
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p1 => sp1,
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p2 => sp2,
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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ax => sreg_block(reg_ax),
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ax => sreg_block(reg_ax),
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ay => sreg_block(reg_ay),
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ay => sreg_block(reg_ay),
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az => sreg_block(reg_az),
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az => sreg_block(reg_az),
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| Line 721... |
Line 727... |
sslave_address <= slave_address;
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sslave_address <= slave_address;
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sslave_write <= slave_write;
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sslave_write <= slave_write;
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sslave_read <= slave_read;
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sslave_read <= slave_read;
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sslave_writedata <= slave_writedata;
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sslave_writedata <= slave_writedata;
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sreg_block(reg_vz) <= sp0;
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for i in reg_scalar downto reg_vz loop
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sreg_block(reg_vy) <= sp1;
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sreg_block(reg_vx) <= sp2;
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for i in reg_scalar downto reg_scalar loop
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if sslave_address=i then
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if sslave_address=i then
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if sslave_write='1' then
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if sslave_write='1' then
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sreg_block(i) <= sslave_writedata;
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sreg_block(i) <= sslave_writedata;
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end if;
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end if;
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end if;
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end if;
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| Line 738... |
Line 746... |
end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end process;
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end process;
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! AVALON MEMORY MAPPED SLAVE FINISHED
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--! AVALON MEMORY MAPPED SLAVE FINISHED
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
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--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
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--! Control Register (reg_ctrl) BASE_ADDRESS + 0x0 |
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--! Control Register (reg_ctrl) BASE_ADDRESS + 0x0 |
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