| Line 89... |
Line 89... |
constant reg_vz : integer:=01;
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constant reg_vz : integer:=01;
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constant reg_vy : integer:=02;
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constant reg_vy : integer:=02;
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constant reg_vx : integer:=03;
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constant reg_vx : integer:=03;
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constant reg_scalar : integer:=04;
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constant reg_scalar : integer:=04;
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constant reg_nfetch : integer:=05;
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constant reg_nfetch : integer:=05;
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constant reg_outputcounter : integer:=06;
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constant reg_timercounter : integer:=06;
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constant reg_inputcounter : integer:=07;
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constant reg_inputcounter : integer:=07;
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constant reg_fetchstart : integer:=08;
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constant reg_fetchstart : integer:=08;
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constant reg_sinkstart : integer:=09;
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constant reg_sinkstart : integer:=09;
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constant reg_ax : integer:=10;
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constant reg_ax : integer:=10;
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constant reg_ay : integer:=11;
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constant reg_ay : integer:=11;
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| Line 188... |
Line 188... |
signal zero : std_logic_vector(31 downto 0);
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signal zero : std_logic_vector(31 downto 0);
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|
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--!High Register Bank Control Signals or AKA Load Sync Chain Control
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--!High Register Bank Control Signals or AKA Load Sync Chain Control
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signal sdownload_chain : download_chain;
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signal sdownload_chain : download_chain;
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signal sdownload_start : download_chain;
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signal sdownload_start : download_chain;
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signal srestart_chain : std_logic;
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--!State Machine Hysteresis Control Signals
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--!State Machine Hysteresis Control Signals
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signal sdrain_condition : std_logic;
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signal sdrain_condition : std_logic;
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signal sdrain_burstcount : std_logic_vector(mb downto 0);
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signal sdrain_burstcount : std_logic_vector(mb downto 0);
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signal sdata_fetch_counter : std_logic_vector(reg_nfetch_high downto 0);
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signal sdata_fetch_counter : std_logic_vector(reg_nfetch_high downto 0);
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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| Line 344... |
Line 343... |
sdrain_burstcount <= '1'&zero(mb-1 downto 0);
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sdrain_burstcount <= '1'&zero(mb-1 downto 0);
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--! Flow Control: El drenado de datos continuará si el número de datos en la cola es mayor o igual a 2**mb O si hay muy pocos datos y no hay datos transitando por el pipeline.
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--! Flow Control: El drenado de datos continuará si el número de datos en la cola es mayor o igual a 2**mb O si hay muy pocos datos y no hay datos transitando por el pipeline.
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sdrain_condition <= '1';
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sdrain_condition <= '1';
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end if;
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end if;
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--! Restart param load chain
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srestart_chain <= sreg_block(reg_ctrl)(reg_ctrl_irq) and sreg_block(reg_ctrl)(reg_ctrl_rlsc);
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--! Data dumpster: Descaratar dato de upload una vez la interconexión haya enganchado el dato.
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--! Data dumpster: Descaratar dato de upload una vez la interconexión haya enganchado el dato.
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if sm=SINK and master_waitrequest='0' and smaster_write='1' then
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if sm=SINK and master_waitrequest='0' and smaster_write='1' then
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soutb_ack <= '1';
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soutb_ack <= '1';
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else
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else
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soutb_ack <= '0';
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soutb_ack <= '0';
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| Line 384... |
Line 380... |
sreg_block(reg_fetchstart) <= (others => '0');
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sreg_block(reg_fetchstart) <= (others => '0');
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--! Control and Status Register
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--! Control and Status Register
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sreg_block(reg_ctrl) <= (others => '0');
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sreg_block(reg_ctrl) <= (others => '0');
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--! Contador Overall
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--! Contador Overall
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sreg_block(reg_inputcounter) <= (others => '0');
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sreg_block(reg_inputcounter) <= (others => '0');
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sreg_block(reg_outputcounter) <= (others => '0');
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-- sreg_block(reg_timercounter) <= (others => '0');
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--! Address Fetch Counter
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--! Address Fetch Counter
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sreg_block(reg_nfetch) <= (others => '0');
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sreg_block(reg_nfetch) <= (others => '0');
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|
|
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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| Line 396... |
Line 392... |
--! Nevermind the State, discount the incoming valid data counter.
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--! Nevermind the State, discount the incoming valid data counter.
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sdata_fetch_counter <= sdata_fetch_counter-master_readdatavalid;
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sdata_fetch_counter <= sdata_fetch_counter-master_readdatavalid;
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|
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--! Debug Counter.
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--! Debug Counter.
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sreg_block(reg_inputcounter) <= sreg_block(reg_inputcounter) + master_readdatavalid;
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sreg_block(reg_inputcounter) <= sreg_block(reg_inputcounter) + master_readdatavalid;
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sreg_block(reg_outputcounter) <= sreg_block(reg_outputcounter) + soutb_ack;
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--!Timer Counter.
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-- case sm is
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-- when IDLE =>
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-- sreg_block(reg_timercounter) <= sreg_block(reg_timercounter) + 0;
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-- when others =>
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-- sreg_block(reg_timercounter) <= sreg_block(reg_timercounter) + 1;
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-- end case;
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|
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--! Flags
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--! Flags
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|
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case sm is
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case sm is
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| Line 504... |
Line 507... |
--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
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--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
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if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
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if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
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sreg_block(reg_ctrl)<= sslave_writedata;
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sreg_block(reg_ctrl)<= sslave_writedata;
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end if;
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end if;
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when x"5" => sreg_block(reg_nfetch) <= sslave_writedata;
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when x"5" => sreg_block(reg_nfetch) <= sslave_writedata;
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when x"6" => sreg_block(reg_outputcounter) <= sslave_writedata;
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-- when x"6" => sreg_block(reg_timercounter) <= sslave_writedata;
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when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
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when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
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when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
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when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
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when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
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when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
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when others => null;
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when others => null;
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end case;
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end case;
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| Line 519... |
Line 522... |
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--! Flow Control: Existe un número de descargas programadas por el sistema, comenzar a realizarlas.
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--! Flow Control: Existe un número de descargas programadas por el sistema, comenzar a realizarlas.
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--! Ir al estado Source.
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--! Ir al estado Source.
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sm <= SOURCE;
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sm <= SOURCE;
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '1';
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '1';
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|
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else
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else
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
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|
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end if;
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end if;
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end if;
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end if;
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| Line 646... |
Line 648... |
for i in reg_bz downto reg_ax loop
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for i in reg_bz downto reg_ax loop
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sreg_block(i) <= (others => '0');
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sreg_block(i) <= (others => '0');
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end loop;
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end loop;
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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ssync_chain_1 <= '0';
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ssync_chain_1 <= '0';
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if master_readdatavalid='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
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if master_readdatavalid='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' and (sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sreg_block(reg_ctrl)(reg_ctrl_rlsc)='0') then
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--! El dato en la interconexión es valido, se debe enganchar.
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--! El dato en la interconexión es valido, se debe enganchar.
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case sdownload_chain is
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case sdownload_chain is
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when DWAX | DWAXBX =>
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when DWAX | DWAXBX =>
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--! Cargar el operando correspondiente al componente "X" del vector "A"
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--! Cargar el operando correspondiente al componente "X" del vector "A"
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ssync_chain_1 <= '0';
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ssync_chain_1 <= '0';
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| Line 702... |
Line 704... |
sdownload_chain <= DWAX;
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sdownload_chain <= DWAX;
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end if;
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end if;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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--! Ok operation check if operation has ended. If that's the case.
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if srestart_chain='1' then
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elsif sreg_block(reg_ctrl)(reg_ctrl_irq)='1' and sreg_block(reg_ctrl)(reg_ctrl_rlsc)='1' then
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sdownload_chain <= sdownload_start;
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sdownload_chain <= sdownload_start;
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end if;
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end if;
|
|
|
end if;
|
|
end if;
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end if;
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end process;
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end process;
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! AVALON MEMORY MAPPED MASTER FINISHED
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--! AVALON MEMORY MAPPED MASTER FINISHED
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
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| Line 724... |
Line 724... |
begin
|
begin
|
if rst=rstMasterValue then
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if rst=rstMasterValue then
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for i in reg_scalar downto reg_vz loop
|
for i in reg_scalar downto reg_vz loop
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sreg_block(i) <= (others => '0');
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sreg_block(i) <= (others => '0');
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end loop;
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end loop;
|
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sreg_block(reg_timercounter) <= (others => '0');
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slave_readdata <= (others => '0');
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slave_readdata <= (others => '0');
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sslave_address <= (others => '0');
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sslave_address <= (others => '0');
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sslave_writedata <= (others => '0');
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sslave_writedata <= (others => '0');
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sslave_write <= '0';
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sslave_write <= '0';
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sslave_read <= '0';
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sslave_read <= '0';
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| Line 738... |
Line 738... |
sslave_address <= slave_address;
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sslave_address <= slave_address;
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sslave_write <= slave_write;
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sslave_write <= slave_write;
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sslave_read <= slave_read;
|
sslave_read <= slave_read;
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sslave_writedata <= slave_writedata;
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sslave_writedata <= slave_writedata;
|
|
|
for i in reg_scalar downto reg_scalar loop
|
if sslave_write='1' and sslave_address=reg_timercounter then
|
if sslave_address=i then
|
sreg_block(reg_timercounter) <= sslave_writedata;
|
if sslave_write='1' then
|
else
|
sreg_block(i) <= sslave_writedata;
|
sreg_block(reg_timercounter) <= sreg_block(reg_timercounter)+1;
|
end if;
|
end if;
|
|
|
|
if sslave_write='1' and sslave_address=reg_scalar then
|
|
sreg_block(reg_scalar) <= sslave_writedata;
|
|
else
|
|
sreg_block(reg_scalar) <= sreg_block(reg_scalar);
|
end if;
|
end if;
|
end loop;
|
|
|
-- for i in reg_scalar downto reg_scalar loop
|
|
-- if sslave_address=i then
|
|
-- if sslave_write='1' then
|
|
-- sreg_block(i) <= sslave_writedata;
|
|
-- end if;
|
|
-- end if;
|
|
-- end loop;
|
for i in 15 downto 0 loop
|
for i in 15 downto 0 loop
|
if sslave_address=i then
|
if sslave_address=i then
|
if sslave_read='1' then
|
if sslave_read='1' then
|
|
|
if (i<10 and i>3) or i=0 then
|
if (i<10 and i>3) or i=0 then
|
| Line 886... |
Line 898... |
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Result Vector Scalar component (reg_scalar) BASE_ADDRESS + 0x10 |
|
--! Result Vector Scalar component (reg_scalar) BASE_ADDRESS + 0x10 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Scratch Vector 00 (reg_nfetch) BASE_ADDRESS + 0x14 |
|
--! Scratch Vector 00 (reg_nfetch) BASE_ADDRESS + 0x14 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! output Data Counter (reg_outputcounter) BASE_ADDRESS + 0x18 |
|
--! output Data Counter (reg_timercounter) BASE_ADDRESS + 0x18 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Input Data Counter (reg_inputcounter) BASE_ADDRESS + 0x1C |
|
--! Input Data Counter (reg_inputcounter) BASE_ADDRESS + 0x1C |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Data Fetch Start Address (reg_fetchstart) BASE_ADDRESS + 0x20 |
|
--! Data Fetch Start Address (reg_fetchstart) BASE_ADDRESS + 0x20 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
