| Line 126... |
Line 126... |
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constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
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constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
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constant reg_ctrl_ageb : integer:=17; --! A>=B.
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constant reg_ctrl_ageb : integer:=17; --! A>=B.
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constant reg_ctrl_aeb : integer:=18; --! A==B.
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constant reg_ctrl_aeb : integer:=18; --! A==B.
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constant reg_ctrl_aneb : integer:=19; --! A!=B.
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constant reg_ctrl_aneb : integer:=19; --! A!=B.
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constant reg_ctrl_reference : integer:=20; --! If one of the
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constant reg_ctrl_accum_op : integer:=20; --! Acummulative Addition/Sub. User must write in the high word of nfetch how many time should be executed the addition/sub.
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constant reg_ctrl_accum_op : integer:=21; --! Acummulative Addition/Sub. User must write in the high word of nfetch how many time should be executed the addition/sub.
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constant reg_ctrl_sign_switcheroo : integer:=22; --! Sphere distance, magnitude like expression sign switch.
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constant reg_ctrl_dma_ncntg_mode : integer:=23; --! Dma Transfer Non Contigous Mode
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constant reg_ctrl_chunk_size_l : integer:=24; --! Dma Transfer Non Contigous Mode chunk size lower bit;
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constant reg_ctrl_chunk_size_h : integer:=25; --! Dma Transfer Non Contigous Mode chunk size higher bit;
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constant reg_ctrl_hop_len_low : integer:=26; --! Dma Transfer Non Contigous Mode hop length lower bit;
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constant reg_ctrl_hop_len_high : integer:=28; --! Dma Transfer Non Contigous Mode hop length
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constant reg_ctrl_use_sw : integer:=29; --! Its ok to use a SW raytrac. This bit is ignored here, in the HW implementation.
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constant reg_ctrl_use_hw : integer:=30; --! Its ok to use a HW raytrac. This bit is is ignored here, in the HW implementation.
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constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
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constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
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--! Nfetch Reg Mask
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--! Nfetch Reg Mask
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constant reg_nfetch_high : integer:=11; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
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constant reg_nfetch_high : integer:=11; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
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Line 228... |
vy : out std_logic_vector(31 downto 0);
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vy : out std_logic_vector(31 downto 0);
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vz : out std_logic_vector(31 downto 0);
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vz : out std_logic_vector(31 downto 0);
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sc : out std_logic_vector(31 downto 0);
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sc : out std_logic_vector(31 downto 0);
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ack : in std_logic;
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ack : in std_logic;
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empty : out std_logic;
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empty : out std_logic;
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sign_switcheroo : in std_logic;
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dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético.
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pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético.
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);
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);
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end component;
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end component;
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| Line 263... |
Line 275... |
vy => svy,
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vy => svy,
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vz => svz,
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vz => svz,
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sc => ssc,
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sc => ssc,
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ack => sr_ack,
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ack => sr_ack,
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empty => sr_e,
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empty => sr_e,
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sign_switcheroo => sreg_block(reg_ctrl)(reg_ctrl_sign_switcheroo),
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dcs => sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s),
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dcs => sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s),
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sync_chain_1 => ssync_chain_1,
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sync_chain_1 => ssync_chain_1,
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pipeline_pending => spipeline_pending
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pipeline_pending => spipeline_pending
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);
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);
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