URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac_hw.tcl] - Diff between revs 221 and 232

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Rev 221	Rev 232
Line 1...	Line 1...
`# TCL File Generated by Component Editor 11.0`	`# TCL File Generated by Component Editor 11.0`
`# Sun Aug 12 22:31:43 COT 2012`	`# Thu Aug 30 11:19:35 COT 2012`
`# DO NOT MODIFY`	`# DO NOT MODIFY`


`# +-----------------------------------`	`# +-----------------------------------`
`# \|`	`# \|`
`# \| raytrac "raytrac" v1.0`	`# \| raytrac "raytrac" v1.0`
`# \| null 2012.08.12.22:31:43`	`# \| null 2012.08.30.11:19:35`
`# \|`	`# \|`
`# \|`	`# \|`
`# \| J:/code/RtEngineHw/SlaveInterfaceDrive/fp_sgdma/raytrac.vhd`	`# \| J:/code/hworkspace/raytrac/fp_sgdma/raytrac.vhd`
`# \|`	`# \|`
`# \| ./raytrac.vhd syn`	`# \| ./raytrac.vhd syn`
`# \| ./arithpack.vhd syn`	`# \| ./arithpack.vhd syn`
`# \|`	`# \|`
`# +-----------------------------------`	`# +-----------------------------------`
Line 55...	Line 55...
`add_parameter wd INTEGER 32`	`add_parameter wd INTEGER 32`
`set_parameter_property wd DEFAULT_VALUE 32`	`set_parameter_property wd DEFAULT_VALUE 32`
`set_parameter_property wd DISPLAY_NAME wd`	`set_parameter_property wd DISPLAY_NAME wd`
`set_parameter_property wd TYPE INTEGER`	`set_parameter_property wd TYPE INTEGER`
`set_parameter_property wd UNITS None`	`set_parameter_property wd UNITS None`
`set_parameter_property wd ALLOWED_RANGES -2147483648:2147483647`
`set_parameter_property wd AFFECTS_GENERATION false`	`set_parameter_property wd AFFECTS_GENERATION false`
`set_parameter_property wd HDL_PARAMETER true`	`set_parameter_property wd HDL_PARAMETER true`
`add_parameter fd INTEGER 8`	`add_parameter fd INTEGER 8`
`set_parameter_property fd DEFAULT_VALUE 8`	`set_parameter_property fd DEFAULT_VALUE 8`
`set_parameter_property fd DISPLAY_NAME fd`	`set_parameter_property fd DISPLAY_NAME fd`
`set_parameter_property fd TYPE INTEGER`	`set_parameter_property fd TYPE INTEGER`
`set_parameter_property fd UNITS None`	`set_parameter_property fd UNITS None`
`set_parameter_property fd ALLOWED_RANGES -2147483648:2147483647`
`set_parameter_property fd AFFECTS_GENERATION false`	`set_parameter_property fd AFFECTS_GENERATION false`
`set_parameter_property fd HDL_PARAMETER true`	`set_parameter_property fd HDL_PARAMETER true`
`add_parameter mb INTEGER 3`	`add_parameter mb INTEGER 4`
`set_parameter_property mb DEFAULT_VALUE 3`	`set_parameter_property mb DEFAULT_VALUE 4`
`set_parameter_property mb DISPLAY_NAME mb`	`set_parameter_property mb DISPLAY_NAME mb`
`set_parameter_property mb TYPE INTEGER`	`set_parameter_property mb TYPE INTEGER`
`set_parameter_property mb UNITS None`	`set_parameter_property mb UNITS None`
`set_parameter_property mb ALLOWED_RANGES -2147483648:2147483647`
`set_parameter_property mb AFFECTS_GENERATION false`	`set_parameter_property mb AFFECTS_GENERATION false`
`set_parameter_property mb HDL_PARAMETER true`	`set_parameter_property mb HDL_PARAMETER true`
`# \|`	`# \|`
`# +-----------------------------------`	`# +-----------------------------------`

Line 84...	Line 81...
`# \|`	`# \|`
`# \|`	`# \|`
`# +-----------------------------------`	`# +-----------------------------------`

`# +-----------------------------------`	`# +-----------------------------------`
`# \| connection point rtClock`	`# \| connection point clock`
`# \|`	`# \|`
`add_interface rtClock clock end`	`add_interface clock clock end`
`set_interface_property rtClock clockRate 0`	`set_interface_property clock clockRate 0`

`set_interface_property rtClock ENABLED true`	`set_interface_property clock ENABLED true`

`add_interface_port rtClock clk clk Input 1`	`add_interface_port clock clk clk Input 1`
`# \|`	`# \|`
`# +-----------------------------------`	`# +-----------------------------------`

`# +-----------------------------------`	`# +-----------------------------------`
`# \| connection point rtSlave`	`# \| connection point rtSlave`
`# \|`	`# \|`
`add_interface rtSlave avalon end`	`add_interface rtSlave avalon end`
`set_interface_property rtSlave addressAlignment DYNAMIC`	`set_interface_property rtSlave addressAlignment DYNAMIC`
`set_interface_property rtSlave addressUnits WORDS`	`set_interface_property rtSlave addressUnits WORDS`
`set_interface_property rtSlave associatedClock rtClock`	`set_interface_property rtSlave associatedClock clock`
`set_interface_property rtSlave associatedReset rtReset`	`set_interface_property rtSlave associatedReset reset_sink`
`set_interface_property rtSlave burstOnBurstBoundariesOnly false`	`set_interface_property rtSlave burstOnBurstBoundariesOnly false`
`set_interface_property rtSlave explicitAddressSpan 0`	`set_interface_property rtSlave explicitAddressSpan 0`
`set_interface_property rtSlave holdTime 0`	`set_interface_property rtSlave holdTime 0`
`set_interface_property rtSlave isMemoryDevice false`	`set_interface_property rtSlave isMemoryDevice false`
`set_interface_property rtSlave isNonVolatileStorage false`	`set_interface_property rtSlave isNonVolatileStorage false`
Line 129...	Line 126...
`add_interface_port rtSlave slave_writedata writedata Input 32`	`add_interface_port rtSlave slave_writedata writedata Input 32`
`# \|`	`# \|`
`# +-----------------------------------`	`# +-----------------------------------`

`# +-----------------------------------`	`# +-----------------------------------`
`# \| connection point rtReset`
`# \|`
`add_interface rtReset reset end`
`set_interface_property rtReset associatedClock rtClock`
`set_interface_property rtReset synchronousEdges BOTH`

`set_interface_property rtReset ENABLED true`

`add_interface_port rtReset rst reset_n Input 1`
`# \|`
`# +-----------------------------------`

`# +-----------------------------------`
`# \| connection point rtMaster`	`# \| connection point rtMaster`
`# \|`	`# \|`
`add_interface rtMaster avalon start`	`add_interface rtMaster avalon start`
`set_interface_property rtMaster addressUnits SYMBOLS`	`set_interface_property rtMaster addressUnits SYMBOLS`
`set_interface_property rtMaster associatedClock rtClock`	`set_interface_property rtMaster associatedClock clock`
`set_interface_property rtMaster associatedReset rtReset`	`set_interface_property rtMaster associatedReset reset_sink`
`set_interface_property rtMaster burstOnBurstBoundariesOnly false`	`set_interface_property rtMaster burstOnBurstBoundariesOnly false`
`set_interface_property rtMaster doStreamReads false`	`set_interface_property rtMaster doStreamReads false`
`set_interface_property rtMaster doStreamWrites false`	`set_interface_property rtMaster doStreamWrites false`
`set_interface_property rtMaster linewrapBursts false`	`set_interface_property rtMaster linewrapBursts false`
`set_interface_property rtMaster readLatency 0`	`set_interface_property rtMaster readLatency 0`

`set_interface_property rtMaster ENABLED true`	`set_interface_property rtMaster ENABLED true`

`add_interface_port rtMaster master_burstcount burstcount Output 5`	`add_interface_port rtMaster master_address address Output 32`
`add_interface_port rtMaster master_waitrequest waitrequest Input 1`	`add_interface_port rtMaster master_waitrequest waitrequest Input 1`
	`add_interface_port rtMaster master_burstcount burstcount Output 5`
`add_interface_port rtMaster master_read read Output 1`	`add_interface_port rtMaster master_read read Output 1`
`add_interface_port rtMaster master_readdata readdata Input 32`	`add_interface_port rtMaster master_readdata readdata Input 32`
`add_interface_port rtMaster master_readdatavalid readdatavalid Input 1`	`add_interface_port rtMaster master_readdatavalid readdatavalid Input 1`
`add_interface_port rtMaster master_write write Output 1`	`add_interface_port rtMaster master_write write Output 1`
`add_interface_port rtMaster master_writedata writedata Output 32`	`add_interface_port rtMaster master_writedata writedata Output 32`
`add_interface_port rtMaster master_address address Output 32`
`# \|`	`# \|`
`# +-----------------------------------`	`# +-----------------------------------`

`# +-----------------------------------`	`# +-----------------------------------`
`# \| connection point interrupt_sender`	`# \| connection point interrupt_sender`
`# \|`	`# \|`
`add_interface interrupt_sender interrupt end`	`add_interface interrupt_sender interrupt end`
`set_interface_property interrupt_sender associatedAddressablePoint rtSlave`	`set_interface_property interrupt_sender associatedAddressablePoint rtSlave`
`set_interface_property interrupt_sender associatedClock rtClock`	`set_interface_property interrupt_sender associatedClock clock`
`set_interface_property interrupt_sender associatedReset rtReset`	`set_interface_property interrupt_sender associatedReset reset_sink`

`set_interface_property interrupt_sender ENABLED true`	`set_interface_property interrupt_sender ENABLED true`

`add_interface_port interrupt_sender irq irq Output 1`	`add_interface_port interrupt_sender irq irq Output 1`
`# \|`	`# \|`
`# +-----------------------------------`	`# +-----------------------------------`

`No newline at end of file`	`No newline at end of file`
	`# +-----------------------------------`
	`# \| connection point reset_sink`
	`# \|`
	`add_interface reset_sink reset end`
	`set_interface_property reset_sink associatedClock clock`
	`set_interface_property reset_sink synchronousEdges BOTH`

	`set_interface_property reset_sink ENABLED true`

	`add_interface_port reset_sink rst reset_n Input 1`
	`# \|`
	`# +-----------------------------------`

`No newline at end of file`	`No newline at end of file`

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[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac_hw.tcl] - Diff between revs 221 and 232