URL
https://opencores.org/ocsvn/raytrac/raytrac/trunk
[/] [raytrac/] [trunk/] [adder.vhd] - Diff between revs 52 and 67
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 52 |
Rev 67 |
| Line 35... |
Line 35... |
result : out std_logic_vector(width-1 downto 0);
|
result : out std_logic_vector(width-1 downto 0);
|
cout : out std_logic
|
cout : out std_logic
|
);
|
);
|
end adder;
|
end adder;
|
|
|
--! @brief arquitectura del sumador
|
--! @brief Arquitectura del sumador
|
architecture adder_arch of adder is
|
architecture adder_arch of adder is
|
|
|
signal sa,p,g: std_logic_vector(width-1 downto 0);
|
signal sa,p,g: std_logic_vector(width-1 downto 0);
|
signal sCarry: std_logic_vector(width downto 1);
|
signal sCarry: std_logic_vector(width downto 1);
|
|
|
| Line 64... |
Line 64... |
cout <= sCarry(width);
|
cout <= sCarry(width);
|
g<= sa and b;
|
g<= sa and b;
|
p<= sa or b;
|
p<= sa or b;
|
|
|
|
|
--! Si se configura una señal para seleccionar entre suma y resta, se generaró el circuito a continuación.
|
--! Si se configura una señal para seleccionar entre suma y resta, se generará el circuito a continuación.
|
|
|
adder_sub_logic : -- adder substractor logic
|
adder_sub_logic : -- adder substractor logic
|
if substractor_selector = "YES" generate
|
if substractor_selector = "YES" generate
|
a_xor_s:
|
a_xor_s:
|
for i in 0 to width-1 generate
|
for i in 0 to width-1 generate
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.