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--! @file adder.vhd
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-- RAYTRAC
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--! @brief Sumador parametrizable.
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-- Author Julian Andres Guarin
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-- adder.vhd
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-- This file is part of raytrac.
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--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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--! Paquete de definicion estandard de logica. Standard logic definition pack.
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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use work.arithpack.all;
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--! Sumador parametrizable.
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use work.arithpack.all;
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--! La entidad es un sumador parametrizable. Las características parametrizables son el ancho de los sumandos, si se usa un circuito ripple carry adder y si se sintetiza una compuerta xor en la entrada que permita la selección de la operación a realizar (suma o resta).
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--! Las entradas y las salidas son las usuales de un sumador: a y b los sumandos, ci el carry de entrada, cout el carry de salida y el valor de la suma en result. Adicionalmente si se selecciona el parametro substractor_selector como "YES" entonces la entrada s, servirá para seleccionar si el sumador realizará la operacion A+B (s=0) ó A-B (s=0). Finalmente la siguiente tabla sintetiza el comportamiento de la entidad.
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--! \n\n
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--! <table>
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--! <tr><th>substractor_selector</th><th>S</th><th>Operación ejecutada</th></tr> <tr><td>"YES"</td><td>0</td><td>A+B</td></tr> --! <tr><td>"YES"</td><td>1</td><td>A-B</td></tr> <tr><td>Otro valor.</td><td>n/a</td><td>A+B</td></tr></table>
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--! El circuito es combinatorio puro y la propagación de las señales hasta el resultado del ultimo carry tiene un tiempo, el cual debe ser considerado para implementar posteriores etapas de pipe en caso de ser necesario.
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entity adder is
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entity adder is
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generic (
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generic (
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w : integer := 9; --! Ancho de los sumandos
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width : integer := 4;
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carry_logic : string := "CLA"; --! Carry logic, seleccione "CLA" para Carry Look Ahead ó "RCA" para Ripple Carry Adder.
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carry_logic : string := "CLA";
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substractor_selector : string := "YES" --! Al seleccionar este parametro en "YES" se puede usar el sumador para restar a través de la señal s.
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substractor_selector : string := "YES"
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);
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);
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port (
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port (
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a,b : in std_logic_vector(w-1 downto 0); --! Sumandos
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a,b : in std_logic_vector(width-1 downto 0);
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s : in std_logic; --! Selector Suma / Resta
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s,ci : in std_logic;
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ci : in std_logic; --! Datos Carry In.
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result : out std_logic_vector(width-1 downto 0);
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result : out std_logic_vector(w-1 downto 0);--! Resultado de la suma.
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cout : out std_logic
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cout : out std_logic --! Carry out (Overflow).
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);
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);
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end adder;
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end adder;
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--! Arquitectura del sumador parametrizable.
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--! Si se configura el sumador para que s seleccione si se va a realizar una suma ó una resta, entonces se instanciara para cada bit de la entrada a, una compuerta xor. Por cada bit del operando a se realizará la operación lógica ai xor s. El resultado se almacena en la señal sa. Si por el contrario el sumador está configurado para ignorar el selector s, entonces la señal sa se conecta directamente a la entrada a.
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architecture adder_arch of adder is
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architecture adder_arch of adder is
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signal sa,p,g: std_logic_vector(w-1 downto 0);
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signal sa,p,g: std_logic_vector(width-1 downto 0);
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signal sCarry: std_logic_vector(w downto 1);
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signal sCarry: std_logic_vector(width downto 1);
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begin
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begin
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-- Usual Structural Model / wether or not CLA/RCA is used and wether or not add/sub selector is used, this port is always instanced --
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-- Usual Structural Model / wether or not CLA/RCA is used and wether or not add/sub selector is used, this port is always instanced --
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result(0)<= a(0) xor b(0) xor ci;
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result(0)<= a(0) xor b(0) xor ci;
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wide_adder:
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wide_adder:
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if (w>1) generate
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if (width>1) generate
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wide_adder_generate_loop:
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wide_adder_generate_loop:
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for i in 1 to w-1 generate
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for i in 1 to width-1 generate
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result(i) <= a(i) xor b(i) xor sCarry(i);
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result(i) <= a(i) xor b(i) xor sCarry(i);
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end generate wide_adder_generate_loop;
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end generate wide_adder_generate_loop;
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end generate wide_adder;
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end generate wide_adder;
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cout <= sCarry(w);
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cout <= sCarry(width);
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g<= sa and b;
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g<= sa and b;
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p<= sa or b;
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p<= sa or b;
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-- Conditional Instantiation / Adder Substraction Logic --
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-- Conditional Instantiation / Adder Substraction Logic --
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adder_sub_logic : -- adder substractor logic
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adder_sub_logic : -- adder substractor logic
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if substractor_selector = "YES" generate
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if substractor_selector = "YES" generate
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a_xor_s:
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a_xor_s:
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for i in 0 to w-1 generate
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for i in 0 to width-1 generate
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sa(i) <= a(i) xor s;
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sa(i) <= a(i) xor s;
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end generate a_xor_s;
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end generate a_xor_s;
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end generate adder_sub_Logic;
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end generate adder_sub_Logic;
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add_logic: -- just adder.
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add_logic: -- just adder.
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-- Conditional Instantiation / RCA/CLA Logical Blocks Generation --
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-- Conditional Instantiation / RCA/CLA Logical Blocks Generation --
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rca_logic_block_instancing: -- Ripple Carry Adder
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rca_logic_block_instancing: -- Ripple Carry Adder
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if carry_logic="RCA" generate
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if carry_logic="RCA" generate
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--! Generar un bloque de cálculo de Carry, Ripple Carry Adder. carry_logic = "RCA".
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rca_x: rca_logic_block
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rca_x: rca_logic_block
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generic map (w=>w)
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generic map (width=>width)
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port map (
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port map (
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p=>p,
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p=>p,
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g=>g,
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g=>g,
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cin=>ci,
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cin=>ci,
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c=>sCarry
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c=>sCarry
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);
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);
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end generate rca_logic_block_instancing;
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end generate rca_logic_block_instancing;
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cla_logic_block_instancing: -- Carry Lookahead Adder
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cla_logic_block_instancing: -- Carry Lookahead Adder
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if carry_logic="CLA" generate
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if carry_logic="CLA" generate
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--! Generar un bloque de cálculo de Carry, Carry Look Ahead. carry_logic = "CLA".
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cla_x: cla_logic_block
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cla_x: cla_logic_block
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generic map (w=>w)
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generic map (width=>width)
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port map (
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port map (
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p=>p,
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p=>p,
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g=>g,
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g=>g,
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cin=>ci,
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cin=>ci,
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c=>sCarry
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c=>sCarry
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);
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);
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end generate cla_logic_block_instancing;
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end generate cla_logic_block_instancing;
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end adder_arch;
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end adder_arch;
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