| Line 13... |
Line 13... |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- GNU General Public License for more details.
|
-- GNU General Public License for more details.
|
--
|
--
|
-- You should have received a copy of the GNU General Public License
|
-- You should have received a copy of the GNU General Public License
|
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
--! Libreria de definición de segnales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n
|
library ieee;
|
library ieee;
|
|
--! Paquete de definicion estandard de logica.
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.
|
use work.arithpack.all;
|
use work.arithpack.all;
|
entity adder is
|
entity adder is
|
generic (
|
generic (
|
width : integer := 4;
|
width : integer := 4;
|
carry_logic : string := "CLA";
|
carry_logic : string := "CLA";
|
| Line 32... |
Line 35... |
result : out std_logic_vector(width-1 downto 0);
|
result : out std_logic_vector(width-1 downto 0);
|
cout : out std_logic
|
cout : out std_logic
|
);
|
);
|
end adder;
|
end adder;
|
|
|
|
--! @brief arquitectura del sumador
|
architecture adder_arch of adder is
|
architecture adder_arch of adder is
|
|
|
signal sa,p,g: std_logic_vector(width-1 downto 0);
|
signal sa,p,g: std_logic_vector(width-1 downto 0);
|
signal sCarry: std_logic_vector(width downto 1);
|
signal sCarry: std_logic_vector(width downto 1);
|
|
|
| Line 48... |
Line 51... |
|
|
-- Usual Structural Model / wether or not CLA/RCA is used and wether or not add/sub selector is used, this port is always instanced --
|
-- Usual Structural Model / wether or not CLA/RCA is used and wether or not add/sub selector is used, this port is always instanced --
|
|
|
result(0)<= a(0) xor b(0) xor ci;
|
result(0)<= a(0) xor b(0) xor ci;
|
wide_adder:
|
wide_adder:
|
|
|
|
|
if (width>1) generate
|
if (width>1) generate
|
wide_adder_generate_loop:
|
wide_adder_generate_loop:
|
for i in 1 to width-1 generate
|
for i in 1 to width-1 generate
|
result(i) <= a(i) xor b(i) xor sCarry(i);
|
result(i) <= a(i) xor b(i) xor sCarry(i);
|
end generate wide_adder_generate_loop;
|
end generate wide_adder_generate_loop;
|
| Line 59... |
Line 64... |
cout <= sCarry(width);
|
cout <= sCarry(width);
|
g<= sa and b;
|
g<= sa and b;
|
p<= sa or b;
|
p<= sa or b;
|
|
|
|
|
-- Conditional Instantiation / Adder Substraction Logic --
|
--! Si se configura una señal para seleccionar entre suma y resta, se generaró el circuito a continuación.
|
|
|
adder_sub_logic : -- adder substractor logic
|
adder_sub_logic : -- adder substractor logic
|
if substractor_selector = "YES" generate
|
if substractor_selector = "YES" generate
|
a_xor_s:
|
a_xor_s:
|
for i in 0 to width-1 generate
|
for i in 0 to width-1 generate
|
sa(i) <= a(i) xor s;
|
sa(i) <= a(i) xor s;
|
end generate a_xor_s;
|
end generate a_xor_s;
|
end generate adder_sub_Logic;
|
end generate adder_sub_Logic;
|
|
|
add_logic: -- just adder.
|
add_logic: --!Si no se configura una señal de selección entonces sencillamente se conecta a a sa.
|
if substractor_selector = "NO" generate
|
if substractor_selector = "NO" generate
|
sa <= a;
|
sa <= a;
|
end generate add_logic;
|
end generate add_logic;
|
|
|
|
|
|
|
-- Conditional Instantiation / RCA/CLA Logical Blocks Generation --
|
-- Conditional Instantiation / RCA/CLA Logical Blocks Generation --
|
|
|
|
--! Si se selecciona un ripple carry adder se instancia el siguiente circuito
|
rca_logic_block_instancing: -- Ripple Carry Adder
|
rca_logic_block_instancing: -- Ripple Carry Adder
|
if carry_logic="RCA" generate
|
if carry_logic="RCA" generate
|
rca_x: rca_logic_block
|
rca_x: rca_logic_block
|
generic map (width=>width)
|
generic map (width=>width)
|
port map (
|
port map (
|
| Line 89... |
Line 96... |
cin=>ci,
|
cin=>ci,
|
c=>sCarry
|
c=>sCarry
|
);
|
);
|
end generate rca_logic_block_instancing;
|
end generate rca_logic_block_instancing;
|
|
|
|
--! Si se selecciona un Carry Lookahead adder se instancia el siguiente circuito
|
cla_logic_block_instancing: -- Carry Lookahead Adder
|
cla_logic_block_instancing: -- Carry Lookahead Adder
|
if carry_logic="CLA" generate
|
if carry_logic="CLA" generate
|
cla_x: cla_logic_block
|
cla_x: cla_logic_block
|
generic map (width=>width)
|
generic map (width=>width)
|
port map (
|
port map (
|
| Line 102... |
Line 110... |
c=>sCarry
|
c=>sCarry
|
);
|
);
|
end generate cla_logic_block_instancing;
|
end generate cla_logic_block_instancing;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
end adder_arch;
|
end adder_arch;
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
