URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [trunk/] [arithpack.vhd] - Diff between revs 13 and 14

Rev 13	Rev 14
Line 18...	Line 18...
`end component;`	`end component;`

`component opcoder`	`component opcoder`
`port (`	`port (`
`Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);`	`Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);`
`m0f0,m0f1,m1f0m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);`	`m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);`
`opcode,addcode : in std_logic`	`opcode,addcode : in std_logic`
`);`	`);`
`end component;`	`end component;`


Line 50...	Line 50...
`);`	`);`
`end component;`	`end component;`
`component adder`	`component adder`
`generic (`	`generic (`
`w : integer := 4;`	`w : integer := 4;`
`carry_logic := "CLA";`	`carry_logic : string := "CLA";`
`substractor_selector := "YES";`	`substractor_selector : string := "YES"`
`);`	`);`
`port (`	`port (`
`a,b : in std_logic_vector (w-1 downto 0);`	`a,b : in std_logic_vector (w-1 downto 0);`
`s,ci : in std_logic;`	`s,ci : in std_logic;`
`result : out std_logic_vector (w-1 downto 0);`	`result : out std_logic_vector (w-1 downto 0);`