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component clock_gen
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component clock_gen
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generic (tclk : time := 20 ns);
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generic (tclk : time := 20 ns);
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port (clk,rst : out std_logic);
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port (clk,rst : out std_logic);
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end component;
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end component;
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--! Ray Trac: Implementacion del Rt Engine
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component raytrac
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generic (
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registered : string := "NO" --! Este parametro, por defecto "YES", indica si se registran o cargan en registros los vectores A,B,C,D y los codigos de operacion opcode y addcode en vez de ser conectados directamente al circuito combinatorio. \n This parameter, by default "YES", indicates if vectors A,B,C,D and operation code inputs opcode are to be loaded into a register at the beginning of the pipe rather than just connecting them to the operations decoder (opcoder).
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);
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port (
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A,B,C,D : in std_logic_vector(18*3-1 downto 0); --! Vectores de entrada A,B,C,D, cada uno de tamano fijo: 3 componentes x 18 bits. \n Input vectors A,B,C,D, each one of fixed size: 3 components x 18 bits.
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opcode,addcode : in std_logic; --! Opcode and addcode input bits, opcode selects what operation is going to perform one of the entities included in the design and addcode what operands are going to be involved in such. \n Opcode & addcode, opcode selecciona que operacion se va a llevar a cabo dentro de una de las entidades referenciadas dentro de la descripcion, mientras que addcode decide cuales van a ser los operandos que realizaran tal.
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clk,rst,ena : in std_logic; --! Las senales de control usual. The usual control signals.
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CPX,CPY,CPZ,DP0,DP1 : out std_logic_vector(31 downto 0) --! Salidas que representan los resultados del RayTrac: pueden ser dos resultados, de dos operaciones de producto punto, o un producto cruz. Por favor revisar el documento de especificacion del dispositivo para tener mas claridad.\n Outputs representing the result of the RayTrac entity: can be the results of two parallel dot product operations or the result of a single cross product, in order to clarify refere to the entity specification documentation.
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);
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end component;
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--! Componente memoria instanciado mediante la biblioteca de altera
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component altsyncram
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component altsyncram
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generic (
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generic (
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address_aclr_a : string;
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address_aclr_a : string;
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clock_enable_input_a : string;
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clock_enable_input_a : string;
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clock_enable_output_a : string;
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clock_enable_output_a : string;
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